From: Luke Kenneth Casson Leighton Date: Tue, 25 May 2021 11:45:59 +0000 (+0000) Subject: increase not-connected pads by one X-Git-Tag: LS180_RC3~47 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02a4319d25253005d8241e199d87db6192495bc9;p=soclayout.git increase not-connected pads by one --- diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v index 25561dd..1bac26f 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -1,16 +1,7 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 12:58:35 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-25 12:45:15 //-------------------------------------------------------------------------------- module ls180( - output wire i2c_scl, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_oe, - input wire uart_tx, - input wire uart_rx, - input wire [15:0] gpio_i, - output wire [15:0] gpio_o, - output wire [15:0] gpio_oe, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -23,6 +14,12 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, + input wire uart_tx, + input wire uart_rx, + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, output wire spimaster_clk, output wire spimaster_mosi, output wire spimaster_cs_n, @@ -30,6 +27,9 @@ module ls180( input wire eint_0, input wire eint_1, input wire eint_2, + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, input wire sys_clk, input wire sys_rst, input wire [1:0] sys_clksel_i, @@ -39,7 +39,7 @@ module ls180( input wire jtag_tck, input wire jtag_tdi, output wire jtag_tdo, - input wire [34:0] nc + input wire [35:0] nc ); (* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0; @@ -159,15 +159,6 @@ wire [63:0] libresocsim_libresoc3; wire libresocsim_libresoc_pll_vco_o; wire [1:0] libresocsim_libresoc_clk_sel; wire libresocsim_libresoc_pll_test_o; -wire libresocsim_libresoc_constraintmanager_i2c_scl; -wire libresocsim_libresoc_constraintmanager_i2c_sda_i; -wire libresocsim_libresoc_constraintmanager_i2c_sda_o; -wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; -reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; -reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; -wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -180,6 +171,12 @@ reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; +reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; +wire libresocsim_libresoc_constraintmanager_i2c_scl; +wire libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; @@ -187,6 +184,9 @@ wire libresocsim_libresoc_constraintmanager_spimaster_miso; wire libresocsim_libresoc_constraintmanager_eint_0; wire libresocsim_libresoc_constraintmanager_eint_1; wire libresocsim_libresoc_constraintmanager_eint_2; +wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r; @@ -1071,8 +1071,8 @@ reg [7:0] gpio1_pads_gpio1i = 8'd0; reg [7:0] gpio1_pads_gpio1o = 8'd0; reg [7:0] gpio1_pads_gpio1oe = 8'd0; reg [2:0] eint_tmp = 3'd0; -wire [34:0] nc_1; -reg [34:0] dummy = 35'd0; +wire [35:0] nc_1; +reg [35:0] dummy = 36'd0; wire i2c_scl_1; wire i2c_oe; wire i2c_sda0; @@ -1618,12 +1618,12 @@ end assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]}; always @(*) begin libresocsim_interface0_converted_interface_cyc <= 1'd0; - subfragments_converter0_next_state <= 1'd0; libresocsim_interface0_converted_interface_stb <= 1'd0; - libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; libresocsim_libresoc_ibus_ack <= 1'd0; - libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; + subfragments_converter0_next_state <= 1'd0; libresocsim_interface0_converted_interface_we <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; + libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; libresocsim_converter0_skip <= 1'd0; libresocsim_interface0_converted_interface_adr <= 30'd0; libresocsim_interface0_converted_interface_sel <= 4'd0; @@ -1677,16 +1677,16 @@ always @(*) begin end assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]}; always @(*) begin + subfragments_converter1_next_state <= 1'd0; libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; - libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; libresocsim_converter1_skip <= 1'd0; + libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; libresocsim_libresoc_dbus_ack <= 1'd0; libresocsim_interface1_converted_interface_adr <= 30'd0; libresocsim_interface1_converted_interface_sel <= 4'd0; libresocsim_interface1_converted_interface_cyc <= 1'd0; libresocsim_interface1_converted_interface_stb <= 1'd0; libresocsim_interface1_converted_interface_we <= 1'd0; - subfragments_converter1_next_state <= 1'd0; subfragments_converter1_next_state <= subfragments_converter1_state; case (subfragments_converter1_state) 1'd1: begin @@ -2115,9 +2115,9 @@ always @(*) begin sdram_bankmachine0_cmd_valid <= 1'd0; sdram_bankmachine0_row_open <= 1'd0; sdram_bankmachine0_row_close <= 1'd0; - subfragments_bankmachine0_next_state <= 3'd0; sdram_bankmachine0_cmd_payload_cas <= 1'd0; sdram_bankmachine0_cmd_payload_ras <= 1'd0; + subfragments_bankmachine0_next_state <= 3'd0; sdram_bankmachine0_cmd_payload_we <= 1'd0; sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; @@ -2273,8 +2273,8 @@ always @(*) begin sdram_bankmachine1_req_wdata_ready <= 1'd0; sdram_bankmachine1_req_rdata_valid <= 1'd0; sdram_bankmachine1_refresh_gnt <= 1'd0; - subfragments_bankmachine1_next_state <= 3'd0; sdram_bankmachine1_cmd_valid <= 1'd0; + subfragments_bankmachine1_next_state <= 3'd0; sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; sdram_bankmachine1_row_open <= 1'd0; sdram_bankmachine1_row_close <= 1'd0; @@ -2430,9 +2430,9 @@ always @(*) begin sdram_bankmachine2_cmd_payload_we <= 1'd0; sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; - subfragments_bankmachine2_next_state <= 3'd0; sdram_bankmachine2_cmd_payload_is_read <= 1'd0; sdram_bankmachine2_cmd_payload_is_write <= 1'd0; + subfragments_bankmachine2_next_state <= 3'd0; sdram_bankmachine2_req_wdata_ready <= 1'd0; sdram_bankmachine2_req_rdata_valid <= 1'd0; sdram_bankmachine2_refresh_gnt <= 1'd0; @@ -2582,9 +2582,9 @@ assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankm assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready); always @(*) begin - subfragments_bankmachine3_next_state <= 3'd0; sdram_bankmachine3_row_open <= 1'd0; sdram_bankmachine3_row_close <= 1'd0; + subfragments_bankmachine3_next_state <= 3'd0; sdram_bankmachine3_cmd_payload_cas <= 1'd0; sdram_bankmachine3_cmd_payload_ras <= 1'd0; sdram_bankmachine3_cmd_payload_we <= 1'd0; @@ -2800,8 +2800,8 @@ assign sdram_dfi_p0_reset_n = 1'd1; assign sdram_dfi_p0_cke = {1{sdram_steerer0}}; assign sdram_dfi_p0_odt = {1{sdram_steerer1}}; always @(*) begin - sdram_en0 <= 1'd0; subfragments_multiplexer_next_state <= 3'd0; + sdram_en0 <= 1'd0; sdram_choose_req_want_writes <= 1'd0; sdram_en1 <= 1'd0; sdram_choose_req_want_reads <= 1'd0; @@ -2932,8 +2932,8 @@ always @(*) begin wb_sdram_ack <= 1'd0; subfragments_next_state <= 1'd0; converter_counter_subfragments_next_value <= 1'd0; - converter_counter_subfragments_next_value_ce <= 1'd0; litedram_wb_adr <= 30'd0; + converter_counter_subfragments_next_value_ce <= 1'd0; litedram_wb_sel <= 2'd0; litedram_wb_cyc <= 1'd0; litedram_wb_stb <= 1'd0; @@ -3168,6 +3168,8 @@ assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe; assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0; assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i; always @(*) begin + libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0; + libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0; libresocsim_libresocsim_wishbone_dat_r <= 32'd0; libresocsim_next_state <= 2'd0; @@ -3175,8 +3177,6 @@ always @(*) begin libresocsim_libresocsim_wishbone_ack <= 1'd0; libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0; libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0; - libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0; - libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; libresocsim_next_state <= libresocsim_state; case (libresocsim_state) 1'd1: begin @@ -3318,9 +3318,9 @@ assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresoc assign libresocsim_shared_err = (((((((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | interface0_converted_interface_err) | interface1_converted_interface_err) | interface2_converted_interface_err) | interface3_converted_interface_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err); assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack)); always @(*) begin + libresocsim_error <= 1'd0; libresocsim_shared_dat_r <= 32'd0; libresocsim_shared_ack <= 1'd0; - libresocsim_error <= 1'd0; libresocsim_shared_ack <= (((((((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | interface0_converted_interface_ack) | interface1_converted_interface_ack) | interface2_converted_interface_ack) | interface3_converted_interface_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack); libresocsim_shared_dat_r <= (((((((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & interface0_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & interface1_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[6]}} & interface2_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[7]}} & interface3_converted_interface_dat_r)) | ({32{libresocsim_slave_sel_r[8]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[9]}} & libresocsim_libresocsim_wishbone_dat_r)); if (libresocsim_done) begin @@ -4519,6 +4519,7 @@ always @(posedge sys_clk_1) begin dummy[32] <= (nc_1[32] | libresocsim_libresoc_interrupt[0]); dummy[33] <= (nc_1[33] | libresocsim_libresoc_interrupt[0]); dummy[34] <= (nc_1[34] | libresocsim_libresoc_interrupt[0]); + dummy[35] <= (nc_1[35] | libresocsim_libresoc_interrupt[0]); if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin libresocsim_converter0_dat_r <= libresocsim_libresoc_ibus_dat_r; end @@ -5650,7 +5651,7 @@ always @(posedge sys_clk_1) begin gpio1_oe_re <= 1'd0; gpio1_out_storage <= 8'd0; gpio1_out_re <= 1'd0; - dummy <= 35'd0; + dummy <= 36'd0; i2c_storage <= 3'd0; i2c_re <= 1'd0; subfragments_converter0_state <= 1'd0;