From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 18:59:34 +0000 (+0100)
Subject: debugging branch fast registers
X-Git-Tag: div_pipeline~641
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02b48044aa8110a9e40a8a46104cf31e3b6a1fe1;p=soc.git

debugging branch fast registers
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index a3d8d9b6..e50d1ca5 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -62,7 +62,8 @@ class DecodeA(Elaboratable):
         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
         with m.If((op.internal_op == InternalOp.OP_BC) |
                   (op.internal_op == InternalOp.OP_BCREG)):
-            with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
+            with m.If(~self.dec.BO[2] |        # 3.0B p38 BO2=0, use CTR reg
+                       self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
                 comb += self.fast_out.ok.eq(1)
 
@@ -156,13 +157,13 @@ class DecodeB(Elaboratable):
 
         # decode SPR2 based on instruction type
         op = self.dec.op
-        # BCREG implicitly uses CTR or LR for 2nd reg
-        with m.If(op.internal_op == InternalOp.OP_BCREG):
-            with m.If(self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
-                comb += self.fast_out.data.eq(FastRegs.CTR)
-            with m.Else():
+        # BCREG implicitly uses LR or TAR for 2nd reg (TODO: TAR)
+        # CTR however is already in fast_spr1 *not* 2.
+        with m.If((op.internal_op == InternalOp.OP_BC) |
+                 (op.internal_op == InternalOp.OP_BCREG)):
+            with m.If(~self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
                 comb += self.fast_out.data.eq(FastRegs.LR)
-            comb += self.fast_out.ok.eq(1)
+                comb += self.fast_out.ok.eq(1)
 
         return m
 
diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index e29f0374..f8481db3 100644
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -95,6 +95,6 @@ class BranchPipeSpec(CommonPipeSpec):
     opsubsetkls = CompBROpSubset
     def rdflags(self, e): # in order of regspec
         cr1_en = e.read_cr1.ok # CR A
-        spr1_ok = e.read_spr1.ok # SPR1
-        spr2_ok = e.read_spr2.ok # SPR2
-        return Cat(spr1_ok, spr2_ok, cr1_en, 1) # CIA CR SPR1 SPR2
+        fast1_ok = e.read_fast1.ok # SPR1
+        fast2_ok = e.read_fast2.ok # SPR2
+        return Cat(fast1_ok, fast2_ok, cr1_en, 1) # SPR1 SPR2 CR CIA
diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py
index c8d02b67..312d3348 100644
--- a/src/soc/fu/compunits/test/test_branch_compunit.py
+++ b/src/soc/fu/compunits/test/test_branch_compunit.py
@@ -36,23 +36,24 @@ class BranchTestRunner(TestRunner):
 
         # CIA (PC)
         res['cia'] = sim.pc.CIA.value
+
         # CR A
         cr1_en = yield dec2.e.read_cr1.ok
         if cr1_en:
             cr1_sel = yield dec2.e.read_cr1.data
             res['cr_a'] = sim.crl[cr1_sel].get_range().value
 
-        # SPR1
-        spr_ok = yield dec2.e.read_spr1.ok
-        spr_num = yield dec2.e.read_spr1.data
+        # Fast1
+        spr_ok = yield dec2.e.read_fast1.ok
+        spr_num = yield dec2.e.read_fast1.data
         # HACK
         spr_num = fast_reg_to_spr(spr_num)
         if spr_ok:
             res['spr1'] = sim.spr[spr_dict[spr_num].SPR].value
 
         # SPR2
-        spr_ok = yield dec2.e.read_spr2.ok
-        spr_num = yield dec2.e.read_spr2.data
+        spr_ok = yield dec2.e.read_fast2.ok
+        spr_num = yield dec2.e.read_fast2.data
         # HACK
         spr_num = fast_reg_to_spr(spr_num)
         if spr_ok: