From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 10 Mar 2020 10:09:56 +0000 (+0100)
Subject: targets/icebreaker: create CRG after SoC.
X-Git-Tag: 24jan2021_ls180~579
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02cba41d644dbb9e4df53f5f2fd176e0bbbbbbbd;p=litex.git

targets/icebreaker: create CRG after SoC.
---

diff --git a/litex/boards/targets/icebreaker.py b/litex/boards/targets/icebreaker.py
index b8045b0c..f58827a1 100755
--- a/litex/boards/targets/icebreaker.py
+++ b/litex/boards/targets/icebreaker.py
@@ -71,12 +71,12 @@ class BaseSoC(SoCCore):
         # Set CPU variant / reset address
         kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
 
-        # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
-
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
 
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
         # 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
         self.submodules.spram = Up5kSPRAM(size=64*kB)
         self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB)