From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 8 May 2020 23:01:22 +0000 (+0100)
Subject: add comments
X-Git-Tag: div_pipeline~1325
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02d9e7000168c563a77696d760fc7547cfc9db4a;p=soc.git

add comments
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index a692a57a..021ac8ab 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -14,7 +14,7 @@ class ALUInputStage(PipeModBase):
         super().__init__(pspec, "input")
 
     def ispec(self):
-        return ALUInputData(self.pspec)
+        return ALUInputData(self.pspec) # XXX TODO, change to ALUFirstInputData
 
     def ospec(self):
         return ALUInputData(self.pspec)
@@ -33,6 +33,8 @@ class ALUInputStage(PipeModBase):
 
         comb += self.o.a.eq(a)
 
+        # TODO: remove this because it's handled by the Computational Unit?
+
         # If there's an immediate, set the B operand to that
         with m.If(self.i.ctx.op.imm_data.imm_ok):
             comb += self.o.b.eq(self.i.ctx.op.imm_data.imm)