From: schwigi <48810576+schwigi@users.noreply.github.com>
Date: Thu, 9 Jan 2020 10:09:35 +0000 (+0100)
Subject: vendor.intel: fix output enable width for XDR=0 case.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02dc4e0515792285de00d2d5b1ba9874e6c72043;p=nmigen.git

vendor.intel: fix output enable width for XDR=0 case.

Fixes #297.
---

diff --git a/nmigen/vendor/intel.py b/nmigen/vendor/intel.py
index bc6e9b4..7ff366d 100644
--- a/nmigen/vendor/intel.py
+++ b/nmigen/vendor/intel.py
@@ -221,8 +221,9 @@ class IntelPlatform(TemplatedPlatform):
 
     @staticmethod
     def _get_oereg(m, pin):
+        # altiobuf_ requires an output enable signal for each pin, but pin.oe is 1 bit wide.
         if pin.xdr == 0:
-            return pin.oe
+            return Repl(pin.oe, pin.width)
         elif pin.xdr in (1, 2):
             oe_reg = Signal(pin.width, name="{}_oe_reg".format(pin.name))
             oe_reg.attrs["useioff"] = "1"
@@ -283,7 +284,7 @@ class IntelPlatform(TemplatedPlatform):
             p_use_oe="TRUE",
             i_datain=self._get_oreg(m, pin, invert),
             o_dataout=port,
-            i_oe=pin.oe,
+            i_oe=self._get_oereg(m, pin)
         )
         return m