From: lkcl <lkcl@web>
Date: Wed, 5 Oct 2022 16:44:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~149
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02eadff41338fa3fad73e80dab208fe21057b37e;p=libreriscv.git

---

diff --git a/nlnet_2022_ongoing/discussion.mdwn b/nlnet_2022_ongoing/discussion.mdwn
index 8efa5d758..d5df4452e 100644
--- a/nlnet_2022_ongoing/discussion.mdwn
+++ b/nlnet_2022_ongoing/discussion.mdwn
@@ -32,8 +32,9 @@ tasks removing, to fit. we cannot risk committing to tasks at too low a
 rate to be able to attract interest and committment.
 
 Again however I do not have a problem with reducing the scope of this one
-to only EUR 50,000 to cover some of the less ambitious tasks, and the
-necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) first.
+to only EUR 50,000 to cover some of the less ambitious tasks, with the
+necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) being first
+priority then a second Grant following up to continue.
 
 **
     What would be the concrete (high level) outcome of that project -
@@ -43,10 +44,12 @@ necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) first.
 
 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 based Routing completed in order to tackle lower geometries (even 90nm),
-https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049 - and sky130
-is far too small an allocation (12 mm^2 when we need around 100).
-Given the amount of time it took (I have to admit it was a major time-sink for me)
-I am happy to wait until coriolis2 is more feature-ready.  Powerful FPGAs
+https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049.
+sky130
+is far too small an allocation (12 mm^2 when we need around 100), we
+really need sky90 which as i understand is still being negotiated and set up.
+Given the amount of time ls180 took (I have to admit it was a major time-sink for me)
+I am happy to wait until coriolis2 is more feature-ready.  Powerful FPGAs will
 get us a long way.
 
 The concrete outcomes:
@@ -55,11 +58,13 @@ The concrete outcomes:
   Abstraction of its core Language Features.  Opportunities then open up
   to perform strict type checking, length checking, other types of Arithmetic
   (Complex numbers, Galois Field) and other "filters" as
-  3rd party extensions, of which the Dynamic SIMD Partitioning created under
+  3rd party extensions, of which the Dynamic SIMD Partitioning Library created under
   2019-02-012 would be the first big showcase.
 * A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
-  Proofs using modern FOSSHW tools is a big deal in its own right. The only
-  other Libre Formal Proof is for an older version of IEEE754, we will
+  Proofs using modern FOSSHW tools (smt2, symbiyosis) is a big deal in its own right.
+  The only
+  other Libre Formal Proof is Academically developed 
+  for an older version of IEEE754: we will
   target 2008 and 2019 semantics.
 * An actual "on-the-ground" realisation of Simple-V in a useable Core, whereas at
   present it is Simulations only and the cavatools Cycle-accurate Simulator
@@ -70,3 +75,5 @@ The concrete outcomes:
   an IBM POWER9 Server which lends us credibility but it needs to be put to
   good use!
 
+In other words, mostly "low-level strategic outcomes" on the way to success :)
+