From: Bill Schmidt Date: Fri, 8 Jul 2016 15:42:47 +0000 (+0000) Subject: re PR target/71297 (ICE on invalid code in altivec_resolve_overloaded_builtin (rs6000... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02eb5b8bf36e8ed4bc234cbadd84aacfe12cb458;p=gcc.git re PR target/71297 (ICE on invalid code in altivec_resolve_overloaded_builtin (rs6000-c.c:5106) on powerpc64le-linux) [gcc] 2016-07-08 Bill Schmidt PR target/71297 * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): Allow standard error handling to take over when a wrong number of arguments is presented to __builtin_vec_ld () or __builtin_vec_st (). [gcc/testsuite] 2016-07-08 Bill Schmidt PR target/71297 * gcc.target/powerpc/pr71297.c: New. From-SVN: r238168 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1cde3326930..9897bfce656 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2016-07-08 Bill Schmidt + + PR target/71297 + * config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): + Allow standard error handling to take over when a wrong number + of arguments is presented to __builtin_vec_ld () or + __builtin_vec_st (). + 2016-07-08 Jiong Wang * config/aarch64/aarch64-simd-builtins.def (smax): Remove float diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 4500668ed9f..fe6db2c097a 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -5281,10 +5281,11 @@ assignment for unaligned loads and stores"); are able to honor __restrict__, for example. We may want to consider this for all memory access built-ins. - When -maltivec=be is specified, simply punt to existing - built-in processing. */ + When -maltivec=be is specified, or the wrong number of arguments + is provided, simply punt to existing built-in processing. */ if (fcode == ALTIVEC_BUILTIN_VEC_LD - && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)) + && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG) + && nargs == 2) { tree arg0 = (*arglist)[0]; tree arg1 = (*arglist)[1]; @@ -5354,7 +5355,8 @@ assignment for unaligned loads and stores"); /* Similarly for stvx. */ if (fcode == ALTIVEC_BUILTIN_VEC_ST - && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG)) + && (BYTES_BIG_ENDIAN || !VECTOR_ELT_ORDER_BIG) + && nargs == 3) { tree arg0 = (*arglist)[0]; tree arg1 = (*arglist)[1]; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0cbcb8896a2..4f107b1af51 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-07-08 Bill Schmidt + + PR target/71297 + * gcc.target/powerpc/pr71297.c: New. + 2016-07-08 Jiong Wang * gcc.target/aarch64/simd/vminmaxnm_1.c: New. diff --git a/gcc/testsuite/gcc.target/powerpc/pr71297.c b/gcc/testsuite/gcc.target/powerpc/pr71297.c new file mode 100644 index 00000000000..db1aaf016cd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr71297.c @@ -0,0 +1,10 @@ +/* PR target/71763 */ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ + +int main () +{ + __builtin_vec_st (); /* { dg-error "too few arguments to function" } */ + +} +