From: Carl Love Date: Thu, 9 Jan 2020 19:37:18 +0000 (-0600) Subject: RS6000, add VSX mask manipulation support X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02ef74bad652522a2e424f3ffafff2452c4da105;p=gcc.git RS6000, add VSX mask manipulation support gcc/ChangeLog 2020-07-09 Carl Love * config/rs6000/vsx.md (VSX_MM): New define_mode_iterator. (VSX_MM4): New define_mode_iterator. (vec_mtvsrbmi): New define_insn. (vec_mtvsr_): New define_insn. (vec_cntmb_): New define_insn. (vec_extract_): New define_insn. (vec_expand_): New define_insn. (define_c_enum unspec): Add entries UNSPEC_MTVSBM, UNSPEC_VCNTMB, UNSPEC_VEXTRACT, UNSPEC_VEXPAND. * config/rs6000/altivec.h ( vec_genbm, vec_genhm, vec_genwm, vec_gendm, vec_genqm, vec_cntm, vec_expandm, vec_extractm): Add defines. * config/rs6000/rs6000-builtin.def: Add defines BU_P10_2, BU_P10_1. (BU_P10_1): Add definitions for mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, vexpandmb, vexpandmh, vexpandmw, vexpandmd, vexpandmq, vextractmb, vextractmh, vextractmw, vextractmd, vextractmq. (BU_P10_2): Add definitions for cntmbb, cntmbh, cntmbw, cntmbd. (BU_P10_OVERLOAD_1): Add definitions for mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm, vexpandm, vextractm. (BU_P10_OVERLOAD_2): Add defition for cntm. * config/rs6000/rs6000-call.c (rs6000_expand_binop_builtin): Add checks for CODE_FOR_vec_cntmbb_v16qi, CODE_FOR_vec_cntmb_v8hi, CODE_FOR_vec_cntmb_v4si, CODE_FOR_vec_cntmb_v2di. (altivec_overloaded_builtins): Add overloaded argument entries for P10_BUILTIN_VEC_MTVSRBM, P10_BUILTIN_VEC_MTVSRHM, P10_BUILTIN_VEC_MTVSRWM, P10_BUILTIN_VEC_MTVSRDM, P10_BUILTIN_VEC_MTVSRQM, P10_BUILTIN_VEC_VCNTMBB, P10_BUILTIN_VCNTMBB, P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW, P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB, P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW, P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ, P10_BUILTIN_VEXTRACTMB, P10_BUILTIN_VEXTRACTMH, P10_BUILTIN_VEXTRACTMW, P10_BUILTIN_VEXTRACTMD, P10_BUILTIN_VEXTRACTMQ. (builtin_function_type): Add case entries for P10_BUILTIN_MTVSRBM, P10_BUILTIN_MTVSRHM, P10_BUILTIN_MTVSRWM, P10_BUILTIN_MTVSRDM, P10_BUILTIN_MTVSRQM, P10_BUILTIN_VCNTMBB, P10_BUILTIN_VCNTMBH, P10_BUILTIN_VCNTMBW, P10_BUILTIN_VCNTMBD, P10_BUILTIN_VEXPANDMB, P10_BUILTIN_VEXPANDMH, P10_BUILTIN_VEXPANDMW, P10_BUILTIN_VEXPANDMD, P10_BUILTIN_VEXPANDMQ. * config/rs6000/rs6000-builtin.def (altivec_overloaded_builtins): Add entries for MTVSRBM, MTVSRHM, MTVSRWM, MTVSRDM, MTVSRQM, VCNTM, VEXPANDM, VEXTRACTM. gcc/testsuite/ChangeLog 2020-07-09 Carl Love * gcc.target/powerpc/vsx_mask-count-runnable.c: New test case. * gcc.target/powerpc/vsx_mask-expand-runnable.c: New test case. * gcc.target/powerpc/vsx_mask-extract-runnable.c: New test case. * gcc.target/powerpc/vsx_mask-move-runnable.c: New test case. --- diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 0d199393556..6c4312492f1 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -711,6 +711,16 @@ __altivec_scalar_pred(vec_any_nle, #define vec_strir_p(a) __builtin_vec_strir_p (a) #define vec_stril_p(a) __builtin_vec_stril_p (a) + +/* VSX Mask Manipulation builtin. */ +#define vec_genbm __builtin_vec_mtvsrbm +#define vec_genhm __builtin_vec_mtvsrhm +#define vec_genwm __builtin_vec_mtvsrwm +#define vec_gendm __builtin_vec_mtvsrdm +#define vec_genqm __builtin_vec_mtvsrqm +#define vec_cntm __builtin_vec_cntm +#define vec_expandm __builtin_vec_vexpandm +#define vec_extractm __builtin_vec_vextractm #endif #endif /* _ALTIVEC_H */ diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index ee0d787cfa2..f7037552faf 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1128,6 +1128,22 @@ (RS6000_BTC_ ## ATTR /* ATTR */ \ | RS6000_BTC_TERNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P10_1(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_1 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vec" NAME, /* NAME */ \ + RS6000_BTM_P10, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_UNARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ + +#define BU_P10_2(ENUM, NAME, ATTR, ICODE) \ + RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ + "__builtin_vec" NAME, /* NAME */ \ + RS6000_BTM_P10, /* MASK */ \ + (RS6000_BTC_ ## ATTR /* ATTR */ \ + | RS6000_BTC_BINARY), \ + CODE_FOR_ ## ICODE) /* ICODE */ #endif @@ -2720,6 +2736,26 @@ BU_P10V_1 (VSTRIHR_P, "vstrihr_p", CONST, vstrir_p_v8hi) BU_P10V_1 (VSTRIBL_P, "vstribl_p", CONST, vstril_p_v16qi) BU_P10V_1 (VSTRIHL_P, "vstrihl_p", CONST, vstril_p_v8hi) +BU_P10V_1 (MTVSRBM, "mtvsrbm", CONST, vec_mtvsr_v16qi) +BU_P10V_1 (MTVSRHM, "mtvsrhm", CONST, vec_mtvsr_v8hi) +BU_P10V_1 (MTVSRWM, "mtvsrwm", CONST, vec_mtvsr_v4si) +BU_P10V_1 (MTVSRDM, "mtvsrdm", CONST, vec_mtvsr_v2di) +BU_P10V_1 (MTVSRQM, "mtvsrqm", CONST, vec_mtvsr_v1ti) +BU_P10V_2 (VCNTMBB, "cntmbb", CONST, vec_cntmb_v16qi) +BU_P10V_2 (VCNTMBH, "cntmbh", CONST, vec_cntmb_v8hi) +BU_P10V_2 (VCNTMBW, "cntmbw", CONST, vec_cntmb_v4si) +BU_P10V_2 (VCNTMBD, "cntmbd", CONST, vec_cntmb_v2di) +BU_P10V_1 (VEXPANDMB, "vexpandmb", CONST, vec_expand_v16qi) +BU_P10V_1 (VEXPANDMH, "vexpandmh", CONST, vec_expand_v8hi) +BU_P10V_1 (VEXPANDMW, "vexpandmw", CONST, vec_expand_v4si) +BU_P10V_1 (VEXPANDMD, "vexpandmd", CONST, vec_expand_v2di) +BU_P10V_1 (VEXPANDMQ, "vexpandmq", CONST, vec_expand_v1ti) +BU_P10V_1 (VEXTRACTMB, "vextractmb", CONST, vec_extract_v16qi) +BU_P10V_1 (VEXTRACTMH, "vextractmh", CONST, vec_extract_v8hi) +BU_P10V_1 (VEXTRACTMW, "vextractmw", CONST, vec_extract_v4si) +BU_P10V_1 (VEXTRACTMD, "vextractmd", CONST, vec_extract_v2di) +BU_P10V_1 (VEXTRACTMQ, "vextractmq", CONST, vec_extract_v1ti) + /* Overloaded vector builtins for ISA 3.1 (power10). */ BU_P10_OVERLOAD_2 (CLRL, "clrl") BU_P10_OVERLOAD_2 (CLRR, "clrr") @@ -2736,6 +2772,15 @@ BU_P10_OVERLOAD_1 (VSTRIL, "stril") BU_P10_OVERLOAD_1 (VSTRIR_P, "strir_p") BU_P10_OVERLOAD_1 (VSTRIL_P, "stril_p") +BU_P10_OVERLOAD_1 (MTVSRBM, "mtvsrbm") +BU_P10_OVERLOAD_1 (MTVSRHM, "mtvsrhm") +BU_P10_OVERLOAD_1 (MTVSRWM, "mtvsrwm") +BU_P10_OVERLOAD_1 (MTVSRDM, "mtvsrdm") +BU_P10_OVERLOAD_1 (MTVSRQM, "mtvsrqm") +BU_P10_OVERLOAD_2 (VCNTM, "cntm") +BU_P10_OVERLOAD_1 (VEXPANDM, "vexpandm") +BU_P10_OVERLOAD_1 (VEXTRACTM, "vextractm") + /* 1 argument crypto functions. */ BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox_v2di) BU_CRYPTO_1 (VSBOX_BE, "vsbox_be", CONST, crypto_vsbox_v16qi) diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index 213673dfe30..5ec3f2c55ad 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -5635,6 +5635,52 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P10_BUILTIN_VEC_VSTRIR_P, P10_BUILTIN_VSTRIHR_P, RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 }, + { P10_BUILTIN_VEC_MTVSRBM, P10_BUILTIN_MTVSRBM, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTDI, 0, 0 }, + { P10_BUILTIN_VEC_MTVSRHM, P10_BUILTIN_MTVSRHM, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTDI, 0, 0 }, + { P10_BUILTIN_VEC_MTVSRWM, P10_BUILTIN_MTVSRWM, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTDI, 0, 0 }, + { P10_BUILTIN_VEC_MTVSRDM, P10_BUILTIN_MTVSRDM, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTDI, 0, 0 }, + { P10_BUILTIN_VEC_MTVSRQM, P10_BUILTIN_MTVSRQM, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_UINTDI, 0, 0 }, + + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBB, + RS6000_BTI_unsigned_long_long, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 }, + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBH, + RS6000_BTI_unsigned_long_long, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_UINTQI, 0 }, + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBW, + RS6000_BTI_unsigned_long_long, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_UINTQI, 0 }, + { P10_BUILTIN_VEC_VCNTM, P10_BUILTIN_VCNTMBD, + RS6000_BTI_unsigned_long_long, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_UINTQI, 0 }, + + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMB, + RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMH, + RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMW, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMD, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P10_BUILTIN_VEC_VEXPANDM, P10_BUILTIN_VEXPANDMQ, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, + + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMB, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMH, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 0, 0 }, + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMW, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 0, 0 }, + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMD, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 0, 0 }, + { P10_BUILTIN_VEC_VEXTRACTM, P10_BUILTIN_VEXTRACTMQ, + RS6000_BTI_INTSI, RS6000_BTI_unsigned_V1TI, 0, 0 }, + { RS6000_BUILTIN_NONE, RS6000_BUILTIN_NONE, 0, 0, 0, 0 } }; @@ -9040,7 +9086,11 @@ rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target) || icode == CODE_FOR_unpackkf || icode == CODE_FOR_unpacktf || icode == CODE_FOR_unpackif - || icode == CODE_FOR_unpacktd) + || icode == CODE_FOR_unpacktd + || icode == CODE_FOR_vec_cntmb_v16qi + || icode == CODE_FOR_vec_cntmb_v8hi + || icode == CODE_FOR_vec_cntmb_v4si + || icode == CODE_FOR_vec_cntmb_v2di) { /* Only allow 1-bit unsigned literals. */ STRIP_NOPS (arg1); @@ -13672,6 +13722,20 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0, case MISC_BUILTIN_CBCDTD: case VSX_BUILTIN_XVCVSPBF16: case VSX_BUILTIN_XVCVBF16SP: + case P10_BUILTIN_MTVSRBM: + case P10_BUILTIN_MTVSRHM: + case P10_BUILTIN_MTVSRWM: + case P10_BUILTIN_MTVSRDM: + case P10_BUILTIN_MTVSRQM: + case P10_BUILTIN_VCNTMBB: + case P10_BUILTIN_VCNTMBH: + case P10_BUILTIN_VCNTMBW: + case P10_BUILTIN_VCNTMBD: + case P10_BUILTIN_VEXPANDMB: + case P10_BUILTIN_VEXPANDMH: + case P10_BUILTIN_VEXPANDMW: + case P10_BUILTIN_VEXPANDMD: + case P10_BUILTIN_VEXPANDMQ: h.uns_p[0] = 1; h.uns_p[1] = 1; break; diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 42a31a60b0e..f75377135ba 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -263,6 +263,10 @@ ;; Mode attribute to give the suffix for the splat instruction (define_mode_attr VSX_SPLAT_SUFFIX [(V16QI "b") (V8HI "h")]) +;; Iterator for the move to mask instructions +(define_mode_iterator VSX_MM [V16QI V8HI V4SI V2DI V1TI]) +(define_mode_iterator VSX_MM4 [V16QI V8HI V4SI V2DI]) + ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT @@ -347,6 +351,10 @@ UNSPEC_VSX_FIRST_MISMATCH_INDEX UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX UNSPEC_XXGENPCV + UNSPEC_MTVSBM + UNSPEC_VCNTMB + UNSPEC_VEXPAND + UNSPEC_VEXTRACT ]) (define_int_iterator XVCVBF16 [UNSPEC_VSX_XVCVSPBF16 @@ -5729,3 +5737,44 @@ "TARGET_POWER10" " %x0,%x1" [(set_attr "type" "vecfloat")]) + +(define_insn "vec_mtvsrbmi" + [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") + (unspec:V16QI [(match_operand:QI 1 "u6bit_cint_operand" "n")] + UNSPEC_MTVSBM))] + "TARGET_POWER10" + "mtvsrbmi %0,%1" +) + +(define_insn "vec_mtvsr_" + [(set (match_operand:VSX_MM 0 "altivec_register_operand" "=v") + (unspec:VSX_MM [(match_operand:DI 1 "gpc_reg_operand" "r")] + UNSPEC_MTVSBM))] + "TARGET_POWER10" + "mtvsrm %0,%1"; + [(set_attr "type" "vecsimple")]) + +(define_insn "vec_cntmb_" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (unspec:DI [(match_operand:VSX_MM4 1 "altivec_register_operand" "v") + (match_operand:QI 2 "const_0_to_1_operand" "n")] + UNSPEC_VCNTMB))] + "TARGET_POWER10" + "vcntmb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "vec_extract_" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:VSX_MM 1 "altivec_register_operand" "v")] + UNSPEC_VEXTRACT))] + "TARGET_POWER10" + "vextractm %0,%1" + [(set_attr "type" "vecsimple")]) + +(define_insn "vec_expand_" + [(set (match_operand:VSX_MM 0 "vsx_register_operand" "=v") + (unspec:VSX_MM [(match_operand:VSX_MM 1 "vsx_register_operand" "v")] + UNSPEC_VEXPAND))] + "TARGET_POWER10" + "vexpandm %0,%1" + [(set_attr "type" "vecsimple")]) diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c new file mode 100644 index 00000000000..f1e3860ee43 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c @@ -0,0 +1,149 @@ +/* { dg-do run } */ +/* { dg-options "-mcpu=power10 -O2" } */ +/* { dg-require-effective-target power10_hw } */ + +/* Check that the expected 128-bit instructions are generated if the processor + supports the 128-bit integer instructions. */ +/* { dg-final { scan-assembler-times {\mvcntmbb\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvcntmbh\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvcntmbw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvcntmbd\M} 1 } } */ + +#define DEBUG 0 + +#if DEBUG +#include +#include +#endif +#include + +void abort (void); + +int main () +{ + int i, num_elements; + unsigned long long arg1; + + vector unsigned char vbc_result_bi, vbc_expected_result_bi; + vector unsigned short vbc_result_hi, vbc_expected_result_hi; + vector unsigned int vbc_result_wi, vbc_expected_result_wi; + vector unsigned long long vbc_result_di, vbc_expected_result_di; + vector __uint128_t vbc_result_qi, vbc_expected_result_qi; + + unsigned int result_wi, expected_result_wi; + unsigned long long result, expected_result; + const unsigned char mp=1; + vector unsigned char vbc_bi_src; + vector unsigned short vbc_hi_src; + vector unsigned int vbc_wi_src; + vector unsigned long long vbc_di_src; + vector __uint128_t vbc_qi_src; + + /* vcntmbb */ + num_elements = 16; + vbc_bi_src[0] = 0xFF; + vbc_bi_src[1] = 0xFF; + vbc_bi_src[2] = 0x0; + vbc_bi_src[3] = 0x0; + vbc_bi_src[4] = 0x0; + vbc_bi_src[5] = 0x0; + vbc_bi_src[6] = 0xFF; + vbc_bi_src[7] = 0xFF; + vbc_bi_src[8] = 0x0; + vbc_bi_src[9] = 0x0; + vbc_bi_src[10] = 0x0; + vbc_bi_src[11] = 0x0; + vbc_bi_src[12] = 0x0; + vbc_bi_src[13] = 0xFF; + vbc_bi_src[14] = 0xFF; + vbc_bi_src[15] = 0xFF; + + expected_result = 7; + + result = vec_cntm (vbc_bi_src, 1); + /* Note count is put in bits[0:7], IBM numbering, of the 64-bit result */ + result = result >> (64-8); + + if (result != expected_result) { +#if DEBUG + printf("ERROR: char vec_cntm(arg) "); + printf("count %llu does not match expected count = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + /* vcntmhb */ + num_elements = 8; + vbc_hi_src[0] = 0xFFFF; + vbc_hi_src[1] = 0xFFFF; + vbc_hi_src[2] = 0x0; + vbc_hi_src[3] = 0x0; + vbc_hi_src[4] = 0x0; + vbc_hi_src[5] = 0x0; + vbc_hi_src[6] = 0xFFFF; + vbc_hi_src[7] = 0xFFFF; + + expected_result = 4; + + result = vec_cntm (vbc_hi_src, 1); + /* Note count is put in bits[0:6], IBM numbering, of the 64-bit result */ + result = result >> (64-7); + + if (result != expected_result) { +#if DEBUG + printf("ERROR: short vec_cntm(arg) "); + printf("count %llu does not match expected count = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + /* vcntmwb */ + num_elements = 4; + vbc_wi_src[0] = 0xFFFFFFFF; + vbc_wi_src[1] = 0xFFFFFFFF; + vbc_wi_src[2] = 0x0; + vbc_wi_src[3] = 0x0; + + expected_result = 2; + + result = vec_cntm (vbc_wi_src, 1); + /* Note count is put in bits[0:5], IBM numbering, of the 64-bit result */ + result = result >> (64-6); + + if (result != expected_result) { +#if DEBUG + printf("ERROR: word vec_cntm(arg) "); + printf("count %llu does not match expected count = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + /* vcntmdb */ + num_elements = 2; + vbc_di_src[0] = 0xFFFFFFFFFFFFFFFFULL; + vbc_di_src[1] = 0xFFFFFFFFFFFFFFFFULL; + + expected_result = 2; + + result = vec_cntm (vbc_di_src, 1); + /* Note count is put in bits[0:4], IBM numbering, of the 64-bit result */ + result = result >> (64-5); + + if (result != expected_result) { +#if DEBUG + printf("ERROR: double vec_cntm(arg) "); + printf("count %llu does not match expected count = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c new file mode 100644 index 00000000000..0c5695e4807 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c @@ -0,0 +1,194 @@ +/* { dg-do run } */ +/* { dg-options "-mcpu=power10 -O2" } */ +/* { dg-require-effective-target power10_hw } */ + +/* Check that the expected 128-bit instructions are generated if the processor + supports the 128-bit integer instructions. */ +/* { dg-final { scan-assembler-times {\mvexpandbm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvexpandhm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvexpandwm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvexpanddm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvexpandqm\M} 1 } } */ + +#define DEBUG 0 + +#if DEBUG +#include +#include +#endif +#include + +void abort (void); + +int main () +{ + int i, num_elements; + unsigned long long arg1; + + vector unsigned char vbc_result_bi, vbc_expected_result_bi; + vector unsigned short vbc_result_hi, vbc_expected_result_hi; + vector unsigned int vbc_result_wi, vbc_expected_result_wi; + vector unsigned long long vbc_result_di, vbc_expected_result_di; + vector __uint128_t vbc_result_qi, vbc_expected_result_qi; + + unsigned int result_wi, expected_result_wi; + unsigned long long result, expected_result; + const unsigned char mp=1; + vector unsigned char vbc_bi_src; + vector unsigned short vbc_hi_src; + vector unsigned int vbc_wi_src; + vector unsigned long long vbc_di_src; + vector __uint128_t vbc_qi_src; + + /* vexpandbm */ + num_elements = 16; + vbc_bi_src[0] = 0xFF; + vbc_bi_src[1] = 0xFF; + vbc_bi_src[2] = 0x0; + vbc_bi_src[3] = 0x0; + vbc_bi_src[4] = 0x0; + vbc_bi_src[5] = 0x0; + vbc_bi_src[6] = 0xFF; + vbc_bi_src[7] = 0xFF; + vbc_bi_src[8] = 0x0; + vbc_bi_src[9] = 0x0; + vbc_bi_src[10] = 0x0; + vbc_bi_src[11] = 0x0; + vbc_bi_src[12] = 0x0; + vbc_bi_src[13] = 0xFF; + vbc_bi_src[14] = 0xFF; + vbc_bi_src[15] = 0xFF; + + vbc_expected_result_bi[0] = 0xFF; + vbc_expected_result_bi[1] = 0xFF; + vbc_expected_result_bi[2] = 0x0; + vbc_expected_result_bi[3] = 0x0; + vbc_expected_result_bi[4] = 0x0; + vbc_expected_result_bi[5] = 0x0; + vbc_expected_result_bi[6] = 0xFF; + vbc_expected_result_bi[7] = 0xFF; + vbc_expected_result_bi[8] = 0x0; + vbc_expected_result_bi[9] = 0x0; + vbc_expected_result_bi[10] = 0x0; + vbc_expected_result_bi[11] = 0x0; + vbc_expected_result_bi[12] = 0x0; + vbc_expected_result_bi[13] = 0xFF; + vbc_expected_result_bi[14] = 0xFF; + vbc_expected_result_bi[15] = 0xFF; + + vbc_result_bi = vec_expandm (vbc_bi_src); + + for (i = 0; i +#include +#endif +#include + +void abort (void); + +int main () +{ + int i, num_elements; + unsigned long long arg1; + + vector unsigned char vbc_result_bi, vbc_expected_result_bi; + vector unsigned short vbc_result_hi, vbc_expected_result_hi; + vector unsigned int vbc_result_wi, vbc_expected_result_wi; + vector unsigned long long vbc_result_di, vbc_expected_result_di; + vector __uint128_t vbc_result_qi, vbc_expected_result_qi; + + unsigned int result_wi, expected_result_wi; + unsigned long long result, expected_result; + const unsigned char mp=1; + vector unsigned char vbc_bi_src; + vector unsigned short vbc_hi_src; + vector unsigned int vbc_wi_src; + vector unsigned long long vbc_di_src; + vector __uint128_t vbc_qi_src; + +/* vextractbm */ + num_elements = 8; + vbc_bi_src[0] = 0xFF; + vbc_bi_src[1] = 0xFF; + vbc_bi_src[2] = 0x0; + vbc_bi_src[3] = 0x0; + vbc_bi_src[4] = 0x0; + vbc_bi_src[5] = 0x0; + vbc_bi_src[6] = 0xFF; + vbc_bi_src[7] = 0xFF; + vbc_bi_src[8] = 0xFF; + vbc_bi_src[9] = 0xFF; + vbc_bi_src[10] = 0xFF; + vbc_bi_src[11] = 0xFF; + vbc_bi_src[12] = 0xFF; + vbc_bi_src[13] = 0x0; + vbc_bi_src[14] = 0xFF; + vbc_bi_src[15] = 0xFF; + + expected_result_wi = 0b1101111111000011; + + result_wi = vec_extractm (vbc_bi_src); + + if (result_wi != expected_result_wi) { +#if DEBUG + printf("ERROR: short vec_extractm(%d) ", vbc_bi_src); + printf("result %llu does not match expected result = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + /* vextracthm */ + num_elements = 8; + vbc_hi_src[0] = 0xFFFF; + vbc_hi_src[1] = 0xFFFF; + vbc_hi_src[2] = 0x0; + vbc_hi_src[3] = 0x0; + vbc_hi_src[4] = 0x0; + vbc_hi_src[5] = 0x0; + vbc_hi_src[6] = 0xFFFF; + vbc_hi_src[7] = 0xFFFF; + + expected_result_wi = 0b11000011; + + result_wi = vec_extractm (vbc_hi_src); + + if (result_wi != expected_result_wi) { +#if DEBUG + printf("ERROR: short vec_extractm(%d) ", vbc_hi_src); + printf("result %llu does not match expected result = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + /* vextractwm */ + num_elements = 4; + vbc_wi_src[0] = 0xFFFFFFFF; + vbc_wi_src[1] = 0xFFFFFFFF; + vbc_wi_src[2] = 0x0; + vbc_wi_src[3] = 0x0; + + expected_result_wi = 0b0011; + + result_wi = vec_extractm (vbc_wi_src); + + if (result_wi != expected_result_wi) { +#if DEBUG + printf("ERROR: word vec_extractm(%d) ", vbc_wi_src); + printf("result %llu does not match expected result = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + /* vextractdm */ + num_elements = 2; + vbc_di_src[0] = 0xFFFFFFFFFFFFFFFF; + vbc_di_src[1] = 0xFFFFFFFFFFFFFFFF; + + expected_result_wi = 0b11; + + result_wi = vec_extractm (vbc_di_src); + + if (result_wi != expected_result_wi) { +#if DEBUG + printf("ERROR: double vec_extractm(%lld) ", vbc_di_src); + printf("result %llu does not match expected result = %llu\n", + result, expected_result); +#else + abort(); +#endif + } + + /* vextractqm */ + num_elements = 1; + vbc_qi_src[0] = 0x1; + vbc_qi_src[0] = vbc_qi_src[0] << 127; + + expected_result_wi = 1; + + result_wi = vec_extractm (vbc_qi_src); + + if (result_wi != expected_result_wi) { +#if DEBUG + printf("ERROR: quad vec_extractm(arg) "); + printf("result 0x%x does not match expected result = 0x%x\n", + result, expected_result); +#else + abort(); +#endif + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c new file mode 100644 index 00000000000..41dee583e59 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c @@ -0,0 +1,225 @@ +/* { dg-do run } */ +/* { dg-options "-mcpu=power10 -O2" } */ +/* { dg-require-effective-target power10_hw } */ + +/* Check that the expected 128-bit instructions are generated if the processor + supports the 128-bit integer instructions. */ +/* { dg-final { scan-assembler-times {\mmtvsrbm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmtvsrhm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmtvsrwm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmtvsrdm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmtvsrqm\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmtvsrbmi\M} 2 } } */ + +#define DEBUG 0 + +#if DEBUG +#include +#include +#endif +#include + +void abort (void); + +int main () +{ + int i, num_elements; + unsigned long long arg1; + + vector unsigned char vbc_result_bi, vbc_expected_result_bi; + vector unsigned short vbc_result_hi, vbc_expected_result_hi; + vector unsigned int vbc_result_wi, vbc_expected_result_wi; + vector unsigned long long vbc_result_di, vbc_expected_result_di; + vector __uint128_t vbc_result_qi, vbc_expected_result_qi; + + unsigned int result_wi, expected_result_wi; + unsigned long long result, expected_result; + const unsigned char mp=1; + vector unsigned char vbc_bi_src; + vector unsigned short vbc_hi_src; + vector unsigned int vbc_wi_src; + vector unsigned long long vbc_di_src; + vector __uint128_t vbc_qi_src; + + /* mtvsrbmi */ + num_elements = 16; + + for (i = 0; i