From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 16:05:27 +0000 (-0800)
Subject: Handle latch symbols too
X-Git-Tag: yosys-0.9~232^2~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02f603ac1a43f3f98048c146b1950c776f73c070;p=yosys.git

Handle latch symbols too
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 950432578..a2b2f611e 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -186,7 +186,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
     std::string s;
     for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
-        if (c == 'i' || c == 'o') {
+        if (c == 'i' || c == 'l' || c == 'o') {
             f.ignore(1);
             if (!(f >> l1 >> s))
                 log_error("Line %d cannot be interpreted as a symbol entry!\n", line_count);
@@ -202,8 +202,6 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
             module->rename(wire, stringf("\\%s", s.c_str()));
         }
-        else if (c == 'l') {
-        }
         else if (c == 'b' || c == 'j' || c == 'f') {
             // TODO
         }