From: Marc Orr <marc.orr@gmail.com>
Date: Mon, 11 Jun 2012 07:16:43 +0000 (-0400)
Subject: Regression: Fix some bugs in simple-timing-mp-ruby.py.
X-Git-Tag: stable_2012_06_28~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02f8178b44cdbe52b523c7385d56f4744801a589;p=gem5.git

Regression: Fix some bugs in simple-timing-mp-ruby.py.
---

diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 4447967a7..1cab30392 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -77,11 +77,13 @@ Ruby.create_system(options, system)
 assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 
 for (i, cpu) in enumerate(system.cpu):
+    # create the interrupt controller
+    cpu.createInterruptController()
+
     #
     # Tie the cpu ports to the ruby cpu ports
     #
-    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
-    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
+    cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
 
 # -----------------------
 # run simulation