From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 6 Jun 2019 19:04:42 +0000 (-0700)
Subject: Add to CHANGELOG
X-Git-Tag: yosys-0.9~48^2~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=030f1d30e9cd04b4412114bdc93a15a39a4597c4;p=yosys.git

Add to CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index 36b64e111..e67d9c903 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+    - Added "muxpack" pass
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"