From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Nov 2018 12:10:45 +0000 (+0000)
Subject: add comment
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0311c247bada07b07ad5ed8c57acc48cec66e614;p=riscv-isa-sim.git

add comment
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 5db0afe..67ced5e 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -608,6 +608,8 @@ sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
     // normally the result is shuffled down by 32 bits (elwidth==default)
     // however with variable bitwidth we want the top elwidth bits,
     // using the SOURCE registers to determine that width.
+    // specifically: truncation of the result due to a shorter
+    // destination elwidth is NOT our problem.
     uint8_t bitwidth = _insn->src_bitwidth;
     uint64_t vlhs = 0;
     uint64_t vrhs = 0;