From: lkcl <lkcl@web>
Date: Sat, 19 Dec 2020 21:11:22 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1165
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03125cc09381b998552eb44b3a242bb7cdf68449;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index c29571134..1dfa6c0f6 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -28,7 +28,7 @@ For the new fields added in SVP64, instructions that have any of their
 fields set to a reserved value must cause an illegal instruction trap,
 to allow emulation of future instruction sets.
 
-This is unlike OpenPower ISA v3.1, which doesn't require a CPU to trap.
+This is unlike OpenPower ISA v3.1, which in many instances does not require a trap.
 
 # Remapped Encoding (`RM[0:23]`)