From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 31 Dec 2019 02:46:22 +0000 (-0800)
Subject: holes_module to be whitebox
X-Git-Tag: working-ls180~849^2~88
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0317a2b476f5ec78cab35b79a02d166c84c0f53e;p=yosys.git

holes_module to be whitebox
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8eb935e1f..e65b16fc6 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -434,6 +434,8 @@ void prep_holes(RTLIL::Module *module)
 	holes_design->modules_.erase(holes_module->name);
 	holes_module->design = design;
 
+	holes_module->set_bool_attribute(ID::whitebox);
+
 	log_pop();
 }
 
@@ -480,6 +482,14 @@ struct Abc9PrepPass : public Pass {
 		extra_args(args, argidx, design);
 
 		for (auto mod : design->selected_modules()) {
+			if (mod->get_blackbox_attribute())
+				continue;
+
+			if (mod->processes.size() > 0) {
+				log("Skipping module %s as it contains processes.\n", log_id(mod));
+				continue;
+			}
+
 			if (break_scc_mode)
 				break_scc(mod);
 			if (unbreak_scc_mode)