From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 16:45:48 +0000 (-0700)
Subject: Add write address to abc_scc_break of ECP5 dist RAM
X-Git-Tag: working-ls180~1237^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0318860b93f7fa4eee148597811c77d67171e5d3;p=yosys.git

Add write address to abc_scc_break of ECP5 dist RAM
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 98f915777..acfb6960e 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -104,7 +104,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-(* abc_box_id=2, abc_scc_break="DI,WRE" *)
+(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
 module TRELLIS_DPR16X4 (
 	input [3:0] DI,
 	input [3:0] WAD,