From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Wed, 21 Sep 2022 19:35:08 +0000 (+0300)
Subject: pysvp64asm: expand vector register macros
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=031dd059e6a60256691090d7a88c1991f7983aa0;p=openpower-isa.git

pysvp64asm: expand vector register macros
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 29047b11..f242fe5c 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -796,7 +796,7 @@ class SVP64Asm:
         svp64 = self.svp64
         insn_no_comments = insn.partition('#')[0]
         # find first space, to get opcode
-        ls = insn_no_comments.split(' ')
+        ls = insn_no_comments.split()
         opcode = ls[0]
         # now find opcode fields
         fields = ''.join(ls[1:]).split(',')
@@ -1491,6 +1491,13 @@ def macro_subst(macros, txt):
                 log("macro", txt, "replaced", replaced, toreplace, value)
                 txt = replaced
                 continue
+            toreplace = '*%s' % macro
+            if toreplace in txt:
+                again = True
+                replaced = txt.replace(toreplace, '*%s' % value)
+                log("macro", txt, "replaced", replaced, toreplace, value)
+                txt = replaced
+                continue
             toreplace = '(%s)' % macro
             if toreplace in txt:
                 again = True