From: Gabe Black Date: Sat, 27 Jan 2007 06:59:20 +0000 (-0500) Subject: Merge zizzer:/bk/newmem X-Git-Tag: m5_2.0_beta3~245 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0358ccee23072eef0b6448e3170457037682a452;p=gem5.git Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/system.cc: Hand Merge --HG-- extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c --- 0358ccee23072eef0b6448e3170457037682a452 diff --cc src/arch/sparc/isa/decoder.isa index 138485a17,32256a04e..cc6eded1d --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@@ -252,30 -246,32 +252,29 @@@ decode OP default Unknown::unknown( Rd = resTemp = Rs1 + val2 + carryin;}}, {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, - {{(Rs1<63:1> + val2<63:1> + - ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, + {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} ); - 0x1A: umulcc({{ + 0x1A: IntOpCcRes::umulcc({{ uint64_t resTemp; Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; - Y = resTemp<63:32>;}}, - {{0}},{{0}},{{0}},{{0}}); - 0x1B: smulcc({{ + Y = resTemp<63:32>;}}); + 0x1B: IntOpCcRes::smulcc({{ int64_t resTemp; - Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; + Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); - Y = resTemp<63:32>;}}, - {{0}},{{0}},{{0}},{{0}}); + Y = resTemp<63:32>;}}); 0x1C: subccc({{ int64_t resTemp, val2 = Rs2_or_imm13; int64_t carryin = Ccr<0:0>; Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, - {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, + {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, + {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} ); - 0x1D: udivxcc({{ + 0x1D: IntOpCcRes::udivxcc({{ if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; - else Rd = Rs1.udw / Rs2_or_imm13.udw;}} - ,{{0}},{{0}},{{0}},{{0}}); + else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 0x1E: udivcc({{ uint32_t resTemp, val2 = Rs2_or_imm13.udw; int32_t overflow = 0; diff --cc src/arch/sparc/isa/formats/mem/blockmem.isa index 352e963b3,c36fede2e..9795d2342 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@@ -492,18 -491,19 +491,19 @@@ let { pcedCode = '' if (microPc == 1): flag_code = "flags[IsLastMicroOp] = true;" - pcedCode = matcher.sub("RdHigh", code) + pcedCode = "RdLow = uReg0;\n" + pcedCode += matcher.sub("RdHigh", code) else: flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;" - pcedCode = matcher.sub("RdLow", code) + pcedCode = matcher.sub("uReg0", code) - iop = InstObjParams(name, Name, 'TwinMem', pcedCode, - opt_flags, {"ea_code": addrCalcReg, + iop = InstObjParams(name, Name, 'TwinMem', + {"code": pcedCode, "ea_code": addrCalcReg, "fault_check": faultCode, "micro_pc": microPc, - "set_flags": flag_code}) - iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', pcedCode, - opt_flags, {"ea_code": addrCalcImm, + "set_flags": flag_code}, opt_flags) + iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', + {"code": pcedCode, "ea_code": addrCalcImm, "fault_check": faultCode, "micro_pc": microPc, - "set_flags": flag_code}) + "set_flags": flag_code}, opt_flags) decoder_output += BlockMemMicroConstructor.subst(iop) decoder_output += BlockMemMicroConstructor.subst(iop_imm) exec_output += doDualSplitExecute( diff --cc src/arch/sparc/isa/formats/mem/util.isa index 5bb4e1fe6,3b02f58de..dbaabdca4 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@@ -170,10 -169,11 +171,11 @@@ def template LoadInitiateAcc { { Fault fault = NoFault; Addr EA; - uint%(mem_acc_size)s_t Mem; + %(fp_enable_check)s; - %(ea_decl)s; - %(ea_rd)s; + %(op_decl)s; + %(op_rd)s; %(ea_code)s; + DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA); %(fault_check)s; if(fault == NoFault) { diff --cc src/arch/sparc/isa_traits.hh index 8a26334a7,062cc8dd3..64ae6abd8 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@@ -58,8 -58,8 +58,8 @@@ namespace SparcIS // These enumerate all the registers for dependence tracking. enum DependenceTags { - FP_Base_DepTag = 33, - Ctrl_Base_DepTag = 97 + FP_Base_DepTag = 32*3+8, - Ctrl_Base_DepTag = FP_Base_DepTag + 64, ++ Ctrl_Base_DepTag = FP_Base_DepTag + 64 }; // semantically meaningful register indices diff --cc src/arch/sparc/tlb.cc index 86e1cefbe,6ed6f59b6..bc3c39294 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@@ -170,10 -172,12 +172,10 @@@ insertAllLocked freeList.remove(new_entry); if (new_entry->valid && new_entry->used) usedEntries--; - - lookupTable.erase(new_entry->range); + if (new_entry->valid) + lookupTable.erase(new_entry->range); - DPRINTF(TLB, "Using entry: %#X\n", new_entry); - assert(PTE.valid()); new_entry->range.va = va; new_entry->range.size = PTE.size() - 1;