From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 5 Apr 2019 22:46:18 +0000 (-0700)
Subject: Merge branch 'eddie/fix_retime' into xc7srl
X-Git-Tag: yosys-0.9~171^2~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0364a5d811f79364f35b72935fe90bc188229c19;p=yosys.git

Merge branch 'eddie/fix_retime' into xc7srl
---

0364a5d811f79364f35b72935fe90bc188229c19
diff --cc techlibs/xilinx/.synth_xilinx.cc.swn
index 000000000,000000000..a6564691a
new file mode 100644
Binary files differ
diff --cc techlibs/xilinx/.synth_xilinx.cc.swo
index 000000000,000000000..6fc27ed3b
new file mode 100644
Binary files differ
diff --cc techlibs/xilinx/synth_xilinx.cc
index cabf0b76e,397c83ac6..ee8dec9ee
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -113,23 -110,21 +113,23 @@@ struct SynthXilinxPass : public Pas
  		log("        dffsr2dff\n");
  		log("        dff2dffe\n");
  		log("        opt -full\n");
 +		log("        simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n");
 +		log("        shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n");
- 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
+ 		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
  		log("        opt -fast\n");
  		log("\n");
 -		log("    map_luts:\n");
 -		log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
 -		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
 -		log("        clean\n");
 -		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 -		log("\n");
  		log("    map_cells:\n");
  		log("        techmap -map +/xilinx/cells_map.v\n");
  		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
  		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
  		log("        clean\n");
  		log("\n");
 +		log("    map_luts:\n");
- 		log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
- 		log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
++		log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
++		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
 +		log("        clean\n");
- 		log("        techmap -map +/xilinx/lut_map.v\n");
++		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 +		log("\n");
  		log("    check:\n");
  		log("        hierarchy -check\n");
  		log("        stat\n");
@@@ -266,34 -256,30 +266,35 @@@
  			Pass::call(design, "dff2dffe");
  			Pass::call(design, "opt -full");
  
 +			if (!nosrl && !retime) {
 +				Pass::call(design, "simplemap t:$dff t:$dffe");
 +				Pass::call(design, "shregmap -tech xilinx -minlen 3");
 +			}
 +
  			if (vpr) {
- 				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
+ 				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
  			} else {
- 				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
+ 				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
  			}
  
  			Pass::call(design, "hierarchy -check");
  			Pass::call(design, "opt -fast");
  		}
  
 -		if (check_label(active, run_from, run_to, "map_luts"))
 +		if (check_label(active, run_from, run_to, "map_cells"))
  		{
 -			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
 -			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 +			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 +			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 +					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
  			Pass::call(design, "clean");
 -			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
  		}
  
 -		if (check_label(active, run_from, run_to, "map_cells"))
 +		if (check_label(active, run_from, run_to, "map_luts"))
  		{
 -			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 -			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 -					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
++			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
 +			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
  			Pass::call(design, "clean");
- 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
++			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
  		}
  
  		if (check_label(active, run_from, run_to, "check"))