From: William D. Jones <thor0505@comcast.net>
Date: Sat, 21 Nov 2020 16:58:30 +0000 (-0500)
Subject: machxo2: Add FACADE_IO simulation model. More comments on models.
X-Git-Tag: working-ls180~64
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0364ded385e3ba7817a9e466e165a184292c3ef2;p=yosys.git

machxo2: Add FACADE_IO simulation model. More comments on models.
---

diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index 89a66be7f..f09837c13 100644
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -69,10 +69,12 @@ module FACADE_FF #(
 	endgenerate
 endmodule
 
+/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */
 module PFUMX (input ALUT, BLUT, C0, output Z);
 	assign Z = C0 ? ALUT : BLUT;
 endmodule
 
+/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */
 module L6MUX21 (input D0, D1, SD, output Z);
 	assign Z = SD ? D1 : D0;
 endmodule
@@ -141,6 +143,8 @@ module FACADE_SLICE #(
 		end
 	endgenerate
 
+	/* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
+	outputs (in other words, feeds back into FACADE_SLICE). */
 	wire di0 = (REG0_SD == "1") ? M0 : DI0;
 	wire di1 = (REG0_SD == "1") ? M1 : DI1;
 
@@ -151,3 +155,24 @@ module FACADE_SLICE #(
 		.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
 		.REGMODE(REG1_REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
 endmodule
+
+module FACADE_IO #(
+	parameter DIR = "INPUT"
+) (
+	inout PAD,
+	input I, EN,
+	output O
+);
+	generate
+		if (DIR == "INPUT") begin
+			assign O = PAD;
+		end else if (DIR == "OUTPUT") begin
+			assign PAD = EN ? I : 1'bz;
+		end else if (DIR == "BIDIR") begin
+			assign PAD = EN ? I : 1'bz;
+			assign O = PAD;
+		end else begin
+			ERROR_UNKNOWN_IO_MODE error();
+		end
+	endgenerate
+endmodule