From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 15:56:23 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2301
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0367433a2a41a3718a06862ef0c2ca6cf5c9003a;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 4afb0c392..85116aced 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -241,13 +241,13 @@ of magnitude increase in the number of hand-written lines of assembler
 compared to a well-designed Cray-style Vector ISA with a `setvl`
 instruction.
 
-<blockquote>
-*Packed SIMD looped algorithms actually have to
+*<blockquote>
+Packed SIMD looped algorithms actually have to
 contain multiple implementations processing fragments of data at
 different SIMD widths: Cray-style Vectors have just the one, covering not
 just current architectural implementations but future ones with
-wider back-end ALUs as well.*
-</blockquote>
+wider back-end ALUs as well.
+</blockquote>*
 
 Assuming then that variable-length Vectors are obviously desirable,
 it becomes a matter of how, not if.  Both Cray and NEC SX Aurora