From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 10 May 2020 22:55:16 +0000 (-0400)
Subject: Add test for rlwnm
X-Git-Tag: div_pipeline~1294
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=036ce6547890a1b26981f8f65b8220d1620bbdef;p=soc.git

Add test for rlwnm
---

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index bf5a7e24..f58d2a01 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -166,6 +166,15 @@ class ALUTestCase(FHDLTestCase):
         with Program(lst) as program:
             sim = self.run_tst_program(program, initial_regs)
 
+    def test_rlwnm(self):
+        lst = ["rlwnm 3, 1, 2, 20, 6"]
+        initial_regs = [0] * 32
+        initial_regs[1] = random.randint(0, (1<<64)-1)
+        initial_regs[2] = random.randint(0, 63)
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+        
+
     def test_ilang(self):
         rec = CompALUOpSubset()