From: lkcl <lkcl@web>
Date: Wed, 27 Apr 2022 15:11:48 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2555
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=037fd1cd629de245574e6f30f1dbcf76c8ad665d;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index c846fc9e0..55e7ad6c8 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -149,6 +149,8 @@ operations may be used, or, if the shift amount is static,
 to reference an alternate starting point in
 the registers containing the Vector elements
 because SVP64 sits on top of a standard Scalar register file.
+`sv.sld r16.v, r26.v, t1` for example is equivalent to shifting
+by an extra 64 bits.
 
 # Vector Multiply