From: lkcl <lkcl@web>
Date: Wed, 20 Apr 2022 13:00:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2680
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=038056fac729ba23b4f95519096c695d0cdc9ae7;p=libreriscv.git

---

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 9094f2f8f..1a1e5fe68 100644
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -36,12 +36,13 @@ Special Registers Altered:
 
 Pseudo-code:
 
-    <!-- SVP64: RC-as-source and RC-as-dest have separate EXTRA2 -->
-    <!-- RT, RA have EXTRA2 marking. RB is always scalar (r0-31) -->
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
     RT <- sum[64:127]
-    RC <- sum[0:63]
+    RS <- sum[0:63]
 
 Special Registers Altered: