From: Alan Lawrence Date: Tue, 8 Sep 2015 19:24:35 +0000 (+0000) Subject: [AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03873eb98330b17e73ada713f31bcbcd50d74026;p=gcc.git [AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix gcc/: * config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_, aarch64_simd_vec_unpacks_hi_): New insn. (vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn. (vec_unpacks_lo_, vec_unpacks_hi_): New expand. (aarch64_float_extend_lo_v2df): Rename to... (aarch64_float_extend_lo_): this, using VDF and so adding V4SF. * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf. (float_extend_lo): Add v4sf. * config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New. * config/aarch64/iterators.md (VQ_HSF): New iterator. (VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF. (Vwide): New mode_attr. From-SVN: r227551 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f9203d70511..127829c2baa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2015-09-08 Alan Lawrence + + * config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_, + aarch64_simd_vec_unpacks_hi_): New insn. + (vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn. + (vec_unpacks_lo_, vec_unpacks_hi_): New expand. + (aarch64_float_extend_lo_v2df): Rename to... + (aarch64_float_extend_lo_): this, using VDF and so adding V4SF. + + * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf. + (float_extend_lo): Add v4sf. + + * config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New. + * config/aarch64/iterators.md (VQ_HSF): New iterator. + (VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF. + (Vwide): New mode_attr. + 2015-09-08 Alan Lawrence * config/aarch64/aarch64-simd.md (aarch64_simd_dup, diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index c5b46aa1404..2c13cfb0823 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -361,11 +361,12 @@ BUILTIN_VSDQ_I_DI (UNOP, abs, 0) BUILTIN_VDQF (UNOP, abs, 2) - VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf) + BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10) VAR1 (BINOP, float_truncate_hi_, 0, v4sf) VAR1 (BINOP, float_truncate_hi_, 0, v8hf) VAR1 (UNOP, float_extend_lo_, 0, v2df) + VAR1 (UNOP, float_extend_lo_, 0, v4sf) BUILTIN_VDF (UNOP, float_truncate_lo_, 0) /* Implemented by aarch64_ld1. */ diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 426bcb62427..a4eaecae2a0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1692,36 +1692,57 @@ ;; Float widening operations. -(define_insn "vec_unpacks_lo_v4sf" - [(set (match_operand:V2DF 0 "register_operand" "=w") - (float_extend:V2DF - (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "w") - (parallel [(const_int 0) (const_int 1)]) - )))] +(define_insn "aarch64_simd_vec_unpacks_lo_" + [(set (match_operand: 0 "register_operand" "=w") + (float_extend: (vec_select: + (match_operand:VQ_HSF 1 "register_operand" "w") + (match_operand:VQ_HSF 2 "vect_par_cnst_lo_half" "") + )))] "TARGET_SIMD" - "fcvtl\\t%0.2d, %1.2s" + "fcvtl\\t%0., %1." [(set_attr "type" "neon_fp_cvt_widen_s")] ) -(define_insn "aarch64_float_extend_lo_v2df" - [(set (match_operand:V2DF 0 "register_operand" "=w") - (float_extend:V2DF - (match_operand:V2SF 1 "register_operand" "w")))] +(define_expand "vec_unpacks_lo_" + [(match_operand: 0 "register_operand" "") + (match_operand:VQ_HSF 1 "register_operand" "")] "TARGET_SIMD" - "fcvtl\\t%0.2d, %1.2s" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, false); + emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], + operands[1], p)); + DONE; + } +) + +(define_insn "aarch64_simd_vec_unpacks_hi_" + [(set (match_operand: 0 "register_operand" "=w") + (float_extend: (vec_select: + (match_operand:VQ_HSF 1 "register_operand" "w") + (match_operand:VQ_HSF 2 "vect_par_cnst_hi_half" "") + )))] + "TARGET_SIMD" + "fcvtl2\\t%0., %1." [(set_attr "type" "neon_fp_cvt_widen_s")] ) -(define_insn "vec_unpacks_hi_v4sf" - [(set (match_operand:V2DF 0 "register_operand" "=w") - (float_extend:V2DF - (vec_select:V2SF - (match_operand:V4SF 1 "register_operand" "w") - (parallel [(const_int 2) (const_int 3)]) - )))] +(define_expand "vec_unpacks_hi_" + [(match_operand: 0 "register_operand" "") + (match_operand:VQ_HSF 1 "register_operand" "")] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (mode, true); + emit_insn (gen_aarch64_simd_vec_unpacks_lo_ (operands[0], + operands[1], p)); + DONE; + } +) +(define_insn "aarch64_float_extend_lo_" + [(set (match_operand: 0 "register_operand" "=w") + (float_extend: + (match_operand:VDF 1 "register_operand" "w")))] "TARGET_SIMD" - "fcvtl2\\t%0.2d, %1.4s" + "fcvtl\\t%0, %1" [(set_attr "type" "neon_fp_cvt_widen_s")] ) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index c7bfadfa33c..91ada618b79 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -6025,10 +6025,6 @@ vaddlvq_u32 (uint32x4_t a) result; \ }) -/* vcvt_f32_f16 not supported */ - -/* vcvt_high_f32_f16 not supported */ - #define vcvt_n_f32_s32(a, b) \ __extension__ \ ({ \ @@ -13436,6 +13432,12 @@ vcvt_high_f32_f64 (float32x2_t __a, float64x2_t __b) /* vcvt (float -> double). */ +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vcvt_f32_f16 (float16x4_t __a) +{ + return __builtin_aarch64_float_extend_lo_v4sf (__a); +} + __extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) vcvt_f64_f32 (float32x2_t __a) { @@ -13443,6 +13445,12 @@ vcvt_f64_f32 (float32x2_t __a) return __builtin_aarch64_float_extend_lo_v2df (__a); } +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vcvt_high_f32_f16 (float16x8_t __a) +{ + return __builtin_aarch64_vec_unpacks_hi_v8hf (__a); +} + __extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) vcvt_high_f64_f32 (float32x4_t __a) { diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 0210602a840..2bd64c897cf 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -94,6 +94,9 @@ ;; Vector single Float modes. (define_mode_iterator VDQSF [V2SF V4SF]) +;; Quad vector Float modes with half/single elements. +(define_mode_iterator VQ_HSF [V8HF V4SF]) + ;; Modes suitable to use as the return type of a vcond expression. (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) @@ -492,14 +495,18 @@ (V2SI "V2DI") (V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI") (HI "SI") (SI "DI") + (V8HF "V4SF") (V4SF "V2DF") (V4HF "V4SF") (V2SF "V2DF")] - ) -;; Widened mode register suffixes for VD_BHSI/VQW. +;; Widened modes of vector modes, lowercase +(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")]) + +;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") (V2SI "2d") (V16QI "8h") - (V8HI "4s") (V4SI "2d")]) + (V8HI "4s") (V4SI "2d") + (V8HF "4s") (V4SF "2d")]) ;; Widened mode register suffixes for VDW/VQW. (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") @@ -508,9 +515,10 @@ (V4HF ".4s") (V2SF ".2d") (SI "") (HI "")]) -;; Lower part register suffixes for VQW. +;; Lower part register suffixes for VQW/VQ_HSF. (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") - (V4SI "2s")]) + (V4SI "2s") (V8HF "4h") + (V4SF "2s")]) ;; Define corresponding core/FP element mode for each vector mode. (define_mode_attr vw [(V8QI "w") (V16QI "w")