From: lkcl <lkcl@web>
Date: Fri, 10 Sep 2021 14:40:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~166
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=038d3d7192fa9d9448d81e19cf7eef0a12402621;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 25cf68e57..5db0d7cbf 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -127,6 +127,10 @@ Examples of the former type:
   With `CRbit` coming from the SVP64 RM bits 22-23 the bit
   of BF to be tested is identified.
 
+Just as with SVP64 [[sv/branches]] there is the option to truncate
+VL to include the element being tested (`VLi=1`) and to exclude it
+(`VLi=0`).
+
 # Predicate-result Condition Register operations
 
 These are again slightly different compared to SVP64 arithmetic