From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 6 Dec 2012 16:15:47 +0000 (+0100)
Subject: bank/csrgen: interface -> bus
X-Git-Tag: 24jan2021_ls180~3066
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0392dd8ac2d495f2a9a11390a87668737ffc79da;p=litex.git

bank/csrgen: interface -> bus
---

diff --git a/top.py b/top.py
index 33708a9f..419ee9d0 100644
--- a/top.py
+++ b/top.py
@@ -114,13 +114,13 @@ def get():
 	fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
 	asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
 	csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
-		uart0.bank.interface,
-		dfii0.bank.interface,
-		identifier0.bank.interface,
-		timer0.bank.interface,
-		minimac0.bank.interface,
-		fb0.bank.interface,
-		asmiprobe0.bank.interface
+		uart0.bank.bus,
+		dfii0.bank.bus,
+		identifier0.bank.bus,
+		timer0.bank.bus,
+		minimac0.bank.bus,
+		fb0.bank.bus,
+		asmiprobe0.bank.bus
 	])
 	
 	#