From: Cooper Qu Date: Mon, 12 Oct 2020 14:29:09 +0000 (+0800) Subject: CSKY: Fix and add some instructions for VDSPV1. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=039dac293d5df5d933808aa5d946b80fd0a84794;p=binutils-gdb.git CSKY: Fix and add some instructions for VDSPV1. gas/ * config/tc-csky.c (get_operand_value): Add handler for OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. * testsuite/gas/csky/csky_vdsp.d : Fix the disassembling for vector register. opcodes/ * csky-dis.c (csky_output_operand): Add handler for OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum. (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add some instructions for VDSPV1. Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 762bc7cbfc5..5cd5d5a0510 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2020-10-26 Cooper Qu + + * config/tc-csky.c (get_operand_value): Add handler for + OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. + * testsuite/gas/csky/csky_vdsp.d : Fix the disassembling for + vector register. + + 2020-10-26 Lili Cui * testsuite/gas/i386/avx-vnni.d: Change psuedo prefix from diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c index 569fe2bc852..23481b838b1 100644 --- a/gas/config/tc-csky.c +++ b/gas/config/tc-csky.c @@ -3673,6 +3673,17 @@ get_operand_value (struct csky_opcode_info *op, } return TRUE; + case OPRND_TYPE_IMM5b_VSH: + /* For vshri.T and vshli.T. */ + if (is_imm_within_range (oper, 0, 31)) + { + int val = csky_insn.val[csky_insn.idx - 1]; + val = (val << 1) | (val >> 4); + val &= 0x1f; + csky_insn.val[csky_insn.idx - 1] = val; + return TRUE; + } + return FALSE; case OPRND_TYPE_IMM8b_BMASKI: /* For csky v2 bmask, which will transfer to 16bits movi. */ if (is_imm_within_range (oper, 1, 8)) @@ -4240,6 +4251,7 @@ get_operand_value (struct csky_opcode_info *op, case OPRND_TYPE_AREG_WITH_LSHIFT_FPU: return is_reg_lshift_illegal (oper, 1); case OPRND_TYPE_FREG_WITH_INDEX: + case OPRND_TYPE_VREG_WITH_INDEX: if (parse_type_freg (oper, 0)) { if (**oper == '[') diff --git a/gas/testsuite/gas/csky/csky_vdsp.d b/gas/testsuite/gas/csky/csky_vdsp.d index 3af441315b9..97330b01004 100644 --- a/gas/testsuite/gas/csky/csky_vdsp.d +++ b/gas/testsuite/gas/csky/csky_vdsp.d @@ -6,30 +6,30 @@ Disassembly of section \.text: #... -\s*[0-9a-f]*:\s*f8623c02\s*vstrq\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623d02\s*vstrq\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623e02\s*vstrq\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623402\s*vldrq\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623502\s*vldrq\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623602\s*vldrq\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623802\s*vstrd\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623902\s*vstrd\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623a02\s*vstrd\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623002\s*vldrd\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623102\s*vldrd\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8623202\s*vldrd\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) -\s*[0-9a-f]*:\s*f8022412\s*vldq\.8\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022512\s*vldq\.16\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022612\s*vldq\.32\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022c12\s*vstq\.8\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022d12\s*vstq\.16\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022e12\s*vstq\.32\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022022\s*vldd\.8\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022122\s*vldd\.16\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022222\s*vldd\.32\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022822\s*vstd\.8\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022922\s*vstd\.16\s*fr2,\s*\(r2,\s*0x10\) -\s*[0-9a-f]*:\s*f8022a22\s*vstd\.32\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8623c02\s*vstrq\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623d02\s*vstrq\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623e02\s*vstrq\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623402\s*vldrq\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623502\s*vldrq\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623602\s*vldrq\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623802\s*vstrd\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623902\s*vstrd\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623a02\s*vstrd\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623002\s*vldrd\.8\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623102\s*vldrd\.16\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623202\s*vldrd\.32\s*vr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8022412\s*vldq\.8\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022512\s*vldq\.16\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022612\s*vldq\.32\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022c12\s*vstq\.8\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022d12\s*vstq\.16\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022e12\s*vstq\.32\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022022\s*vldd\.8\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022122\s*vldd\.16\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022222\s*vldd\.32\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022822\s*vstd\.8\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022922\s*vstd\.16\s*vr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022a22\s*vstd\.32\s*vr2,\s*\(r2,\s*0x10\) \s*[0-9a-f]*:\s*c43eb020\s*vmulsh\s*r30,\s*r1 \s*[0-9a-f]*:\s*c7e0b040\s*vmulsha\s*r0,\s*r31 \s*[0-9a-f]*:\s*c58cb420\s*vmulsw\s*r12,\s*r12 @@ -43,9 +43,9 @@ Disassembly of section \.text: \s*[0-9a-f]*:\s*f8101305\s*vmtvr.u8\s*vr5\[0\],\s*r16 \s*[0-9a-f]*:\s*f8ea1324\s*vmtvr.u16\s*vr4\[7\],\s*r10 \s*[0-9a-f]*:\s*f9ea134f\s*vmtvr.u32\s*vr15\[15\],\s*r10 -\s*[0-9a-f]*:\s*f94a0e81\s*vdup.8\s*fr1,\s*vr10\[10\] -\s*[0-9a-f]*:\s*f83a0e8f\s*vdup.16\s*fr15,\s*vr10\[1\] -\s*[0-9a-f]*:\s*faaa0e87\s*vdup.32\s*fr7,\s*vr10\[5\] +\s*[0-9a-f]*:\s*f94a0e81\s*vdup.8\s*vr1,\s*vr10\[10\] +\s*[0-9a-f]*:\s*f83a0e8f\s*vdup.16\s*vr15,\s*vr10\[1\] +\s*[0-9a-f]*:\s*faaa0e87\s*vdup.32\s*vr7,\s*vr10\[5\] \s*[0-9a-f]*:\s*f8030c02\s*vmov\s*vr2,\s*vr3 \s*[0-9a-f]*:\s*f8030062\s*vcadd\.eu8\s*vr2,\s*vr3 \s*[0-9a-f]*:\s*f8130062\s*vcadd\.eu16\s*vr2,\s*vr3 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0720b950869..5851a641e77 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2020-10-26 Cooper Qu + + * csky-dis.c (csky_output_operand): Add handler for + OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX. + * csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum. + (OPRND_TYPE_IMM5b_VSH): New enum. (csky_v2_opcodes): Fix and add + some instructions for VDSPV1. + 2020-10-26 Lili Cui * i386-dis.c: Change "XV" to print "{vex}" pseudo prefix. diff --git a/opcodes/csky-dis.c b/opcodes/csky-dis.c index b31b685b905..4916bb6c37a 100644 --- a/opcodes/csky-dis.c +++ b/opcodes/csky-dis.c @@ -415,6 +415,15 @@ csky_output_operand (char *str, struct operand const *oprnd, strcat (str, buf); ret = 0; break; + case OPRND_TYPE_IMM5b_VSH: + { + char num[128]; + value = ((value & 0x1) << 4) | (value >> 1); + sprintf (num, "%d", (int)value); + strcat (str, num); + ret = 0; + break; + } case OPRND_TYPE_MSB2SIZE: case OPRND_TYPE_LSB2SIZE: { @@ -837,7 +846,7 @@ csky_output_operand (char *str, struct operand const *oprnd, else if ((value & 0x3) == 0x3) strcat (str, "3"); break; - case OPRND_TYPE_FREG_WITH_INDEX: + case OPRND_TYPE_VREG_WITH_INDEX: { unsigned freg_val = value & 0xf; unsigned index_val = (value >> 4) & 0xf; @@ -845,6 +854,14 @@ csky_output_operand (char *str, struct operand const *oprnd, strcat(str, buf); break; } + case OPRND_TYPE_FREG_WITH_INDEX: + { + unsigned freg_val = value & 0xf; + unsigned index_val = (value >> 4) & 0xf; + sprintf (buf, "fr%d[%d]", freg_val, index_val); + strcat(str, buf); + break; + } case OPRND_TYPE_REGr4_r7: if (IS_CSKY_V1 (mach_flag)) { diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h index 199b8913717..e309253a18c 100644 --- a/opcodes/csky-opc.h +++ b/opcodes/csky-opc.h @@ -44,6 +44,7 @@ enum operand_type OPRND_TYPE_AREG_WITH_LSHIFT_FPU, OPRND_TYPE_FREG_WITH_INDEX, + OPRND_TYPE_VREG_WITH_INDEX, /* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */ OPRND_TYPE_REG_r1a, /* r1 only, for divs/divu in csky v1 ISA. */ @@ -133,6 +134,7 @@ enum operand_type OPRND_TYPE_IMM5b_LS, /* Operand type for rori and rotri. */ OPRND_TYPE_IMM5b_RORI, + OPRND_TYPE_IMM5b_VSH, OPRND_TYPE_IMM5b_POWER, OPRND_TYPE_IMM5b_7_31_POWER, OPRND_TYPE_IMM5b_BMASKI, @@ -6416,200 +6418,215 @@ const struct csky_opcode csky_v2_opcodes[] = /* The followings are vdsp instructions for ck810. */ OP32 ("vdup.8", OPCODE_INFO2 (0xf8000e80, - (0_3, FREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vdup.16", OPCODE_INFO2 (0xf8100e80, - (0_3, FREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vdup.32", OPCODE_INFO2 (0xfa000e80, - (0_3, FREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vmfvr.u8", OPCODE_INFO2 (0xf8001200, (0_4, AREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vmfvr.u16", OPCODE_INFO2 (0xf8001220, (0_4, AREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vmfvr.u32", OPCODE_INFO2 (0xf8001240, (0_4, AREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vmfvr.s8", OPCODE_INFO2 (0xf8001280, (0_4, AREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vmfvr.s16", OPCODE_INFO2 (0xf80012a0, (0_4, AREG, OPRND_SHIFT_0_BIT), - (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vmtvr.u8", OPCODE_INFO2 (0xf8001300, - (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vmtvr.u16", OPCODE_INFO2 (0xf8001320, - (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), + OP32 ("vins.8", + OPCODE_INFO2 (0xf8001400, + (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vins.16", + OPCODE_INFO2 (0xf8101400, + (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vins.32", + OPCODE_INFO2 (0xfa001400, + (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), OP32 ("vmtvr.u32", OPCODE_INFO2 (0xf8001340, - (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), OP32 ("vldd.8", SOPCODE_INFO2 (0xf8002000, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), CSKY_ISA_VDSP), OP32 ("vldd.16", SOPCODE_INFO2 (0xf8002100, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), CSKY_ISA_VDSP), OP32 ("vldd.32", SOPCODE_INFO2 (0xf8002200, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), CSKY_ISA_VDSP), OP32 ("vldq.8", SOPCODE_INFO2 (0xf8002400, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), CSKY_ISA_VDSP), OP32 ("vldq.16", SOPCODE_INFO2 (0xf8002500, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), CSKY_ISA_VDSP), OP32 ("vldq.32", SOPCODE_INFO2 (0xf8002600, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), CSKY_ISA_VDSP), OP32 ("vstd.8", SOPCODE_INFO2 (0xf8002800, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), CSKY_ISA_VDSP), OP32 ("vstd.16", SOPCODE_INFO2 (0xf8002900, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), CSKY_ISA_VDSP), OP32 ("vstd.32", SOPCODE_INFO2 (0xf8002a00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), CSKY_ISA_VDSP), OP32 ("vstq.8", SOPCODE_INFO2 (0xf8002c00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), CSKY_ISA_VDSP), OP32 ("vstq.16", SOPCODE_INFO2 (0xf8002d00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), CSKY_ISA_VDSP), OP32 ("vstq.32", SOPCODE_INFO2 (0xf8002e00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), CSKY_ISA_VDSP), OP32 ("vldrd.8", SOPCODE_INFO2 (0xf8003000, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vldrd.16", SOPCODE_INFO2 (0xf8003100, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vldrd.32", SOPCODE_INFO2 (0xf8003200, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vldrq.8", SOPCODE_INFO2 (0xf8003400, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vldrq.16", SOPCODE_INFO2 (0xf8003500, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vldrq.32", SOPCODE_INFO2 (0xf8003600, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vstrd.8", SOPCODE_INFO2 (0xf8003800, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vstrd.16", SOPCODE_INFO2 (0xf8003900, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vstrd.32", SOPCODE_INFO2 (0xf8003a00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vstrq.8", SOPCODE_INFO2 (0xf8003c00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vstrq.16", SOPCODE_INFO2 (0xf8003d00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), OP32 ("vstrq.32", SOPCODE_INFO2 (0xf8003e00, - (0_3, FREG, OPRND_SHIFT_0_BIT), + (0_3, VREG, OPRND_SHIFT_0_BIT), BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), CSKY_ISA_VDSP), @@ -7888,6 +7905,84 @@ const struct csky_opcode csky_v2_opcodes[] = (16_19, VREG, OPRND_SHIFT_0_BIT), (21_24, VREG, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), + OP32 ("vshri.u8", + OPCODE_INFO3 (0xf8000600, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.u16", + OPCODE_INFO3 (0xf8100600, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.u32", + OPCODE_INFO3 (0xfa000600, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.s8", + OPCODE_INFO3 (0xf8000610, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.s16", + OPCODE_INFO3 (0xf8100610, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.s32", + OPCODE_INFO3 (0xfa000610, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.u8.r", + OPCODE_INFO3 (0xf8000640, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.u16.r", + OPCODE_INFO3 (0xf8100640, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.u32.r", + OPCODE_INFO3 (0xfa000640, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.s8.r", + OPCODE_INFO3 (0xf8000650, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.s16.r", + OPCODE_INFO3 (0xf8100650, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshri.s32.r", + OPCODE_INFO3 (0xfa000650, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.s32.r", + OPCODE_INFO3 (0xfa0006d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), OP32 ("vshr.s32.r", OPCODE_INFO3 (0xfa0006d0, (0_3, VREG, OPRND_SHIFT_0_BIT), @@ -7966,6 +8061,78 @@ const struct csky_opcode csky_v2_opcodes[] = (16_19, VREG, OPRND_SHIFT_0_BIT), (21_24, VREG, OPRND_SHIFT_0_BIT)), CSKY_ISA_VDSP), + OP32 ("vshli.u8", + OPCODE_INFO3 (0xf8000700, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.u16", + OPCODE_INFO3 (0xf8100700, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.u32", + OPCODE_INFO3 (0xfa000700, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.s8", + OPCODE_INFO3 (0xf8000710, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.s16", + OPCODE_INFO3 (0xf8100710, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.s32", + OPCODE_INFO3 (0xfa000710, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.u8.s", + OPCODE_INFO3 (0xf8000740, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.u16.s", + OPCODE_INFO3 (0xf8100740, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.u32.s", + OPCODE_INFO3 (0xfa000740, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.s8.s", + OPCODE_INFO3 (0xf8000750, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.s16.s", + OPCODE_INFO3 (0xf8100750, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshli.s32.s", + OPCODE_INFO3 (0xfa000750, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), OP32 ("vcmphs.u8", OPCODE_INFO3 (0xf8000800, (0_3, VREG, OPRND_SHIFT_0_BIT),