From: Dmitry Selyutin Date: Mon, 8 Jan 2024 20:26:32 +0000 (+0300) Subject: oppc: rename Assign classes X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03ba57099ddb00dcb4fc0be0dd3f3e69f4ec0aff;p=openpower-isa.git oppc: rename Assign classes --- diff --git a/src/openpower/oppc/pc_ast.py b/src/openpower/oppc/pc_ast.py index 5a8d0a06..d139d2db 100644 --- a/src/openpower/oppc/pc_ast.py +++ b/src/openpower/oppc/pc_ast.py @@ -245,12 +245,12 @@ class AssignIEAOp(Token): pass -class Assign(Dataclass): +class AssignExpr(Dataclass): lvalue: Node rvalue: Node -class AssignIEA(Assign): +class AssignIEAExpr(AssignExpr): lvalue: Node rvalue: Node diff --git a/src/openpower/oppc/pc_parser.py b/src/openpower/oppc/pc_parser.py index 596830ed..03adc635 100644 --- a/src/openpower/oppc/pc_parser.py +++ b/src/openpower/oppc/pc_parser.py @@ -207,9 +207,9 @@ class Parser: else: (lvalue, rvalue) = (p[1], p[3]) if isinstance(p[2], pc_ast.AssignOp): - cls = pc_ast.Assign + cls = pc_ast.AssignExpr else: - cls = pc_ast.AssignIEA + cls = pc_ast.AssignIEAExpr if (isinstance(lvalue, pc_ast.Symbol) and (str(lvalue) in self.__class__.REGS)): lvalue = self.__class__.REGS[str(lvalue)](lvalue) diff --git a/src/openpower/oppc/pc_util.py b/src/openpower/oppc/pc_util.py index e3e184ed..76058ecb 100644 --- a/src/openpower/oppc/pc_util.py +++ b/src/openpower/oppc/pc_util.py @@ -88,11 +88,11 @@ class PseudocodeVisitor(mdis.visitor.ContextVisitor): stmt = f"{node.name}({args})" self[node].emit(stmt=stmt) - @Hook(pc_ast.Assign, pc_ast.AssignIEA) - def Assign(self, node): + @Hook(pc_ast.AssignExpr, pc_ast.AssignIEAExpr) + def AssignExpr(self, node): mapping = { - pc_ast.Assign: "<-", - pc_ast.AssignIEA: "<-iea", + pc_ast.AssignExpr: "<-", + pc_ast.AssignIEAExpr: "<-iea", } yield node lvalue = str(self[node.lvalue])