From: whitequark <cz@m-labs.hk>
Date: Tue, 2 Jul 2019 18:37:02 +0000 (+0000)
Subject: hdl.mem: fix naming of registers inside unnamed memories.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03c64038e8ff74a1f54802671f802a2048557330;p=nmigen.git

hdl.mem: fix naming of registers inside unnamed memories.

Before this commit, `None` would leak into the vcd file with pysim.
---

diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index 2111ecc..45836cb 100644
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -27,7 +27,8 @@ class Memory:
         self._array = Array()
         if simulate:
             for addr in range(self.depth):
-                self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
+                self._array.append(Signal(self.width, name="{}({})"
+                                          .format(name or "memory", addr)))
 
         self.init = init