From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Jan 2020 00:42:16 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
X-Git-Tag: working-ls180~849^2~18
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03ce2c72bb4e8cd32df994dec04815fa5ecec6fe;p=yosys.git

Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
---

03ce2c72bb4e8cd32df994dec04815fa5ecec6fe
diff --cc tests/techmap/abc9.ys
index d5a63e1cb,62b5dfef6..2140dde26
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@@ -39,30 -39,14 +39,43 @@@ design -load gol
  scratchpad -copy abc9.script.flow3 abc9.script
  abc9 -lut 4
  
 +design -reset
 +read_verilog <<EOT
 +module top(input a, b, output o);
 +(* keep *) wire w = a & b;
 +assign o = ~w;
 +endmodule
 +EOT
 +
 +simplemap
 +equiv_opt -assert abc9 -lut 4
 +design -load postopt
 +select -assert-count 2 t:$lut
 +
++
 +design -reset
 +read_verilog -icells <<EOT
 +module top(input a, b, output o);
 +wire w;
 +(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
 +assign o = ~w;
 +endmodule
 +EOT
 +
 +simplemap
 +equiv_opt -assert abc9 -lut 4
 +design -load postopt
 +select -assert-count 1 t:$lut
 +select -assert-count 1 t:$_AND_
++
+ 
+ design -reset
+ read_verilog -icells <<EOT
+ module top(input a, b, output o);
+ assign o = ~(a & b);
+ endmodule
+ EOT
+ abc9 -lut 4
+ clean
+ select -assert-count 1 t:$lut
+ select -assert-none t:$lut t:* %D