From: Jeff Law Date: Wed, 27 Jun 2018 18:30:06 +0000 (-0600) Subject: v850-modes.def (CCZ, CCNZ): Add new modes. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03e32fb74897185119352fa2340782b6d7510024;p=gcc.git v850-modes.def (CCZ, CCNZ): Add new modes. * config/v850/v850-modes.def (CCZ, CCNZ): Add new modes. * config/v850/v850.c (notice_update_cc): Remove. * config/v850/v850.h (CC_OVERFLOW_UNUSABLE): Remove (CC_NO_CARRY): Likewise. (NOTICE_UPDATE_CC): Define to nothing. * config/v850/v850.md: Remove block comment on cc0 handling Remove "cc" attribute from all patterns. Remove cc_status handling from all patterns. Minor formatting fixes. Co-Authored-By: Austin Law From-SVN: r262189 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c6dc2da7e4c..d9abfff5d0c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2018-06-27 Jeff Law + Austin Law + + * config/v850/v850-modes.def (CCZ, CCNZ): Add new modes. + * config/v850/v850.c (notice_update_cc): Remove. + * config/v850/v850.h (CC_OVERFLOW_UNUSABLE): Remove + (CC_NO_CARRY): Likewise. + (NOTICE_UPDATE_CC): Define to nothing. + * config/v850/v850.md: Remove block comment on cc0 handling + Remove "cc" attribute from all patterns. Remove cc_status handling + from all patterns. Minor formatting fixes. + 2018-06-27 Kyrylo Tkachov * config/aarch64/aarch64-cores.def (cortex-a76): New entry. diff --git a/gcc/config/v850/v850-modes.def b/gcc/config/v850/v850-modes.def index ed37c799dd9..5503d6a526f 100644 --- a/gcc/config/v850/v850-modes.def +++ b/gcc/config/v850/v850-modes.def @@ -18,6 +18,8 @@ along with GCC; see the file COPYING3. If not see . */ +CC_MODE (CCZ); +CC_MODE (CCNZ); CC_MODE (CC_FPU_LT); CC_MODE (CC_FPU_LE); CC_MODE (CC_FPU_GT); diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c index 720cce86044..e184718e1ef 100644 --- a/gcc/config/v850/v850.c +++ b/gcc/config/v850/v850.c @@ -1985,55 +1985,6 @@ expand_epilogue (void) v850_interrupt_p = FALSE; } -/* Update the condition code from the insn. */ -void -notice_update_cc (rtx body, rtx_insn *insn) -{ - switch (get_attr_cc (insn)) - { - case CC_NONE: - /* Insn does not affect CC at all. */ - break; - - case CC_NONE_0HIT: - /* Insn does not change CC, but the 0'th operand has been changed. */ - if (cc_status.value1 != 0 - && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1)) - cc_status.value1 = 0; - break; - - case CC_SET_ZN: - /* Insn sets the Z,N flags of CC to recog_data.operand[0]. - V,C is in an unusable state. */ - CC_STATUS_INIT; - cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; - cc_status.value1 = recog_data.operand[0]; - break; - - case CC_SET_ZNV: - /* Insn sets the Z,N,V flags of CC to recog_data.operand[0]. - C is in an unusable state. */ - CC_STATUS_INIT; - cc_status.flags |= CC_NO_CARRY; - cc_status.value1 = recog_data.operand[0]; - break; - - case CC_COMPARE: - /* The insn is a compare instruction. */ - CC_STATUS_INIT; - cc_status.value1 = SET_SRC (body); - break; - - case CC_CLOBBER: - /* Insn doesn't leave CC in a usable state. */ - CC_STATUS_INIT; - break; - - default: - break; - } -} - /* Retrieve the data area that has been chosen for the given decl. */ v850_data_area diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h index 2e737a8de3f..96bddc25801 100644 --- a/gcc/config/v850/v850.h +++ b/gcc/config/v850/v850.h @@ -567,19 +567,7 @@ struct cum_arg { int nbytes; }; #define SELECT_CC_MODE(OP, X, Y) v850_select_cc_mode (OP, X, Y) -/* Tell final.c how to eliminate redundant test instructions. */ - -/* Here we define machine-dependent flags and fields in cc_status - (see `conditions.h'). No extra ones are needed for the VAX. */ - -/* Store in cc_status the expressions - that the condition codes will describe - after execution of an instruction whose pattern is EXP. - Do not alter them if the instruction would not alter the cc's. */ - -#define CC_OVERFLOW_UNUSABLE 0x200 -#define CC_NO_CARRY CC_NO_OVERFLOW -#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN) +#define NOTICE_UPDATE_CC(EXP, INSN) /* Nonzero if access to memory by bytes or half words is no faster than accessing full words. */ diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index 67d906329e8..0fad9ea501d 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -81,17 +81,6 @@ (const_string "v850e3v5")] (const_string "none"))) -;; Condition code settings. -;; none - insn does not affect cc -;; none_0hit - insn does not affect cc but it does modify operand 0 -;; This attribute is used to keep track of when operand 0 changes. -;; See the description of NOTICE_UPDATE_CC for more info. -;; set_znv - sets z,n,v to usable values; c is unknown. -;; set_zn - sets z,n to usable values; v,c is unknown. -;; compare - compare instruction -;; clobber - value of cc is unknown -(define_attr "cc" "none,none_0hit,set_z,set_zn,set_znv,compare,clobber" - (const_string "clobber")) ;; Function units for the V850. As best as I can tell, there's ;; a traditional memory load/use stall as well as a stall if @@ -120,8 +109,7 @@ (match_operand 2 "disp23_operand" "W")))))] "TARGET_V850E2V3_UP" "ld.b %2[%1],%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "unsign23byte_load" [(set (match_operand:SI 0 "register_operand" "=r") @@ -130,8 +118,7 @@ (match_operand 2 "disp23_operand" "W")))))] "TARGET_V850E2V3_UP" "ld.bu %2[%1],%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "sign23hword_load" [(set (match_operand:SI 0 "register_operand" "=r") @@ -140,8 +127,7 @@ (match_operand 2 "disp23_operand" "W")))))] "TARGET_V850E2V3_UP" "ld.h %2[%1],%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "unsign23hword_load" [(set (match_operand:SI 0 "register_operand" "=r") @@ -150,8 +136,7 @@ (match_operand 2 "disp23_operand" "W")))))] "TARGET_V850E2V3_UP" "ld.hu %2[%1],%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "23word_load" [(set (match_operand:SI 0 "register_operand" "=r") @@ -159,8 +144,7 @@ (match_operand 2 "disp23_operand" "W"))))] "TARGET_V850E2V3_UP" "ld.w %2[%1],%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "23byte_store" [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r") @@ -168,8 +152,7 @@ (match_operand:QI 2 "register_operand" "r"))] "TARGET_V850E2V3_UP" "st.b %2,%1[%0]" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "23hword_store" [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r") @@ -177,8 +160,7 @@ (match_operand:HI 2 "register_operand" "r"))] "TARGET_V850E2V3_UP" "st.h %2,%1[%0]" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "23word_store" [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r") @@ -186,8 +168,7 @@ (match_operand:SI 2 "register_operand" "r"))] "TARGET_V850E2V3_UP" "st.w %2,%1[%0]" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) ;; movdi @@ -221,9 +202,7 @@ || (register_operand (operands[0], DImode) && register_operand (operands[1], DImode))" { return v850_gen_movdi (operands); } [(set_attr "length" "4,12,12") - (set_attr "cc" "none_0hit") - (set_attr "type" "other,load,store")] -) + (set_attr "type" "other,load,store")]) ;; movqi @@ -247,7 +226,6 @@ return output_move_single (operands); } [(set_attr "length" "2,4,2,2,4,4,4") - (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,load,other,load,store,store")]) ;; movhi @@ -272,7 +250,6 @@ return output_move_single (operands); } [(set_attr "length" "2,4,2,2,4,4,4") - (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,load,other,load,store,store")]) ;; movsi and helpers @@ -283,7 +260,6 @@ "" "movhi hi(%1),%.,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "other")]) (define_insn "*movsi_lo" @@ -293,7 +269,6 @@ "" "movea lo(%2),%1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "other")]) (define_expand "movsi" @@ -348,7 +323,6 @@ return output_move_single (operands); } [(set_attr "length" "2,4,4,2,2,4,4,4,4,6") - (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,other,load,other,load,other,store,store,other")]) (define_insn "*movsi_internal" @@ -360,7 +334,6 @@ return output_move_single (operands); } [(set_attr "length" "2,4,4,2,2,4,4,4,4") - (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,other,load,other,load,store,store,other")]) (define_insn "*movsf_internal" @@ -372,7 +345,6 @@ return output_move_single (operands); } [(set_attr "length" "2,4,4,8,2,2,4,4,4,8") - (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit") (set_attr "type" "other,other,other,other,load,other,load,store,store,other")]) ;; ---------------------------------------------------------------------- @@ -387,8 +359,7 @@ (const_int 0)))] "" "tst1 %1,%0" - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")]) ;; This replaces ld.b;sar;andi with tst1;setf nz. @@ -445,8 +416,7 @@ "@ cmp %1,%0 cmp %1,%0" - [(set_attr "length" "2,2") - (set_attr "cc" "compare")]) + [(set_attr "length" "2,2")]) (define_expand "cbranchsf4" [(set (pc) @@ -499,8 +469,7 @@ gcc_unreachable (); } [(set_attr "length" "12") - (set_attr "type" "fpu")] -) + (set_attr "type" "fpu")]) (define_expand "cbranchdf4" [(set (pc) @@ -553,8 +522,7 @@ gcc_unreachable (); } [(set_attr "length" "12") - (set_attr "type" "fpu")] -) + (set_attr "type" "fpu")]) (define_expand "cmpsf" [(set (reg:CC CC_REGNUM) @@ -593,8 +561,7 @@ add %2,%0 addi %2,%1,%0 addi %O2(%P2),%1,%0" - [(set_attr "length" "2,4,4") - (set_attr "cc" "set_zn,set_zn,set_zn")]) + [(set_attr "length" "2,4,4")]) ;; ---------------------------------------------------------------------- ;; SUBTRACT INSTRUCTIONS @@ -609,8 +576,7 @@ "@ sub %2,%0 subr %1,%0" - [(set_attr "length" "2,2") - (set_attr "cc" "set_zn,set_zn")]) + [(set_attr "length" "2,2")]) (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") @@ -618,8 +584,7 @@ (clobber (reg:CC CC_REGNUM))] "" "subr %.,%0" - [(set_attr "length" "2") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "2")]) ;; ---------------------------------------------------------------------- ;; MULTIPLY INSTRUCTIONS @@ -647,7 +612,6 @@ "" "mulh %2,%0" [(set_attr "length" "2") - (set_attr "cc" "none_0hit") (set_attr "type" "mult")]) (define_insn "mulhisi3_internal2" @@ -660,7 +624,6 @@ mulh %2,%0 mulhi %2,%1,%0" [(set_attr "length" "2,4") - (set_attr "cc" "none_0hit,none_0hit") (set_attr "type" "mult")]) ;; ??? The scheduling info is probably wrong. @@ -680,7 +643,6 @@ "(TARGET_V850E_UP)" "mul %2,%1,%." [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "mult")]) ;; ---------------------------------------------------------------------- @@ -709,7 +671,6 @@ return "div %2,%0,%3"; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "div")]) (define_insn "udivmodsi4" @@ -728,7 +689,6 @@ return "divu %2,%0,%3"; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "div")]) ;; ??? There is a 2 byte instruction for generating only the quotient. @@ -745,7 +705,6 @@ "TARGET_V850E_UP" "sxh %0\n\tdivh %2,%0,%3" [(set_attr "length" "6") - (set_attr "cc" "clobber") (set_attr "type" "div")]) ;; The half word needs to be zero/sign extended to 32 bits before doing @@ -762,7 +721,6 @@ "TARGET_V850E_UP" "zxh %0\n\tdivhu %2,%0,%3" [(set_attr "length" "6") - (set_attr "cc" "clobber") (set_attr "type" "div")]) ;; ---------------------------------------------------------------------- @@ -784,7 +742,6 @@ return ""; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "*v850_clr1_2" @@ -806,7 +763,6 @@ return ""; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "*v850_clr1_3" @@ -827,7 +783,6 @@ return ""; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "andsi3" @@ -840,8 +795,7 @@ and %2,%0 and %.,%0 andi %2,%1,%0" - [(set_attr "length" "2,2,4") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "2,2,4")]) ;; ---------------------------------------------------------------------- ;; OR INSTRUCTIONS @@ -855,7 +809,6 @@ "" "set1 %M1,%0" [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "*v850_set1_2" @@ -880,7 +833,6 @@ return ""; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "*v850_set1_3" @@ -906,7 +858,6 @@ return ""; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "iorsi3" @@ -919,8 +870,7 @@ or %2,%0 or %.,%0 ori %2,%1,%0" - [(set_attr "length" "2,2,4") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "2,2,4")]) ;; ---------------------------------------------------------------------- ;; XOR INSTRUCTIONS @@ -934,7 +884,6 @@ "" "not1 %M1,%0" [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "*v850_not1_2" @@ -959,7 +908,6 @@ return ""; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "*v850_not1_3" @@ -985,7 +933,6 @@ return ""; } [(set_attr "length" "4") - (set_attr "cc" "clobber") (set_attr "type" "bit1")]) (define_insn "xorsi3" @@ -998,8 +945,7 @@ xor %2,%0 xor %.,%0 xori %2,%1,%0" - [(set_attr "length" "2,2,4") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "2,2,4")]) ;; ---------------------------------------------------------------------- ;; NOT INSTRUCTIONS @@ -1011,8 +957,7 @@ (clobber (reg:CC CC_REGNUM))] "" "not %1,%0" - [(set_attr "length" "2") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "2")]) ;; ----------------------------------------------------------------- ;; BIT FIELDS @@ -1035,9 +980,7 @@ (match_operand:SI 3 "register_operand" "r"))] "TARGET_V850E3V5_UP" "bins %3, %2, %1, %0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")] -) + [(set_attr "length" "4")]) ;; ----------------------------------------------------------------- ;; Scc INSTRUCTIONS @@ -1048,18 +991,8 @@ (match_operator:SI 1 "comparison_operator" [(cc0) (const_int 0)]))] "" -{ - if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 - && (GET_CODE (operands[1]) == GT - || GET_CODE (operands[1]) == GE - || GET_CODE (operands[1]) == LE - || GET_CODE (operands[1]) == LT)) - return 0; - - return "setf %c1,%0"; -} - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + "setf %c1,%0" + [(set_attr "length" "4")]) (define_insn "setf_insn" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1067,24 +1000,21 @@ [(reg:CC CC_REGNUM) (const_int 0)]))] "" "setf %b1,%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "set_z_insn" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand 1 "v850_float_z_comparison_operator" ""))] "TARGET_V850E2V3_UP" "setf z,%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) (define_insn "set_nz_insn" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand 1 "v850_float_nz_comparison_operator" ""))] "TARGET_V850E2V3_UP" "setf nz,%0" - [(set_attr "length" "4") - (set_attr "cc" "none_0hit")]) + [(set_attr "length" "4")]) ;; ---------------------------------------------------------------------- ;; CONDITIONAL MOVE INSTRUCTIONS @@ -1150,8 +1080,7 @@ (match_operand:SI 3 "reg_or_0_operand" "rI")))] "(TARGET_V850E_UP)" "cmov %c1,%2,%z3,%0"; - [(set_attr "length" "6") - (set_attr "cc" "compare")]) + [(set_attr "length" "6")]) (define_insn "movsicc_reversed_cc" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1162,8 +1091,7 @@ (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] "(TARGET_V850E_UP)" "cmov %C1,%3,%z2,%0" - [(set_attr "length" "6") - (set_attr "cc" "compare")]) + [(set_attr "length" "6")]) (define_insn "*movsicc_normal" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1175,8 +1103,7 @@ (match_operand:SI 3 "reg_or_0_operand" "rI")))] "(TARGET_V850E_UP)" "cmp %5,%4 ; cmov %c1,%2,%z3,%0" - [(set_attr "length" "6") - (set_attr "cc" "clobber")]) + [(set_attr "length" "6")]) (define_insn "*movsicc_reversed" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1188,8 +1115,7 @@ (match_operand:SI 3 "reg_or_int5_operand" "rJ")))] "(TARGET_V850E_UP)" "cmp %5,%4 ; cmov %C1,%3,%z2,%0" - [(set_attr "length" "6") - (set_attr "cc" "clobber")]) + [(set_attr "length" "6")]) (define_insn "*movsicc_tst1" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1204,8 +1130,7 @@ (match_operand:SI 5 "reg_or_0_operand" "rI")))] "(TARGET_V850E_UP)" "tst1 %3,%2 ; cmov %c1,%4,%z5,%0" - [(set_attr "length" "8") - (set_attr "cc" "clobber")]) + [(set_attr "length" "8")]) (define_insn "*movsicc_tst1_reversed" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1220,8 +1145,7 @@ (match_operand:SI 5 "reg_or_int5_operand" "rJ")))] "(TARGET_V850E_UP)" "tst1 %3,%2 ; cmov %C1,%5,%z4,%0" - [(set_attr "length" "8") - (set_attr "cc" "clobber")]) + [(set_attr "length" "8")]) ;; Matching for sasf requires combining 4 instructions, so we provide a ;; dummy pattern to match the first 3, which will always be turned into the @@ -1239,8 +1163,7 @@ (clobber (reg:CC CC_REGNUM))] "(TARGET_V850E_UP)" "cmp %4,%3 ; sasf %c1,%0" - [(set_attr "length" "6") - (set_attr "cc" "clobber")]) + [(set_attr "length" "6")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -1293,8 +1216,7 @@ (clobber (reg:CC CC_REGNUM))] "(TARGET_V850E_UP)" "bsh %1,%0" - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")]) (define_expand "rotlsi3" [(parallel [(set (match_operand:SI 0 "register_operand" "") @@ -1316,9 +1238,7 @@ (match_operand:SI 3 "const_int_operand" "n"))]))] "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)" "rotl %2, %1, %0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")] -) + [(set_attr "length" "4")]) (define_insn "rotlsi3_b" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1329,9 +1249,7 @@ (match_operand:SI 2 "const_int_operand" "n"))]))] "TARGET_V850E3V5_UP && (INTVAL (operands[2]) + INTVAL (operands[3]) == 32)" "rotl %2, %1, %0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")] -) + [(set_attr "length" "4")]) (define_insn "rotlsi3_v850e3v5" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1340,9 +1258,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_V850E3V5_UP" "rotl %2, %1, %0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")] -) + [(set_attr "length" "4")]) (define_insn "*rotlsi3_16" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1351,8 +1267,7 @@ (clobber (reg:CC CC_REGNUM))] "(TARGET_V850E_UP)" "hsw %1,%0" - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")]) ;; ---------------------------------------------------------------------- ;; JUMP INSTRUCTIONS @@ -1384,9 +1299,7 @@ default: gcc_unreachable (); } } - [(set_attr "length" "2,6") - (set_attr "cc" "none")] -) + [(set_attr "length" "2,6")]) (define_expand "doloop_end" [(use (match_operand 0 "" "")) ; loop pseudo @@ -1432,8 +1345,7 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 65534)) (const_int 4) - (const_int 14))) - (set_attr "cc" "none")]) + (const_int 14)))]) ;; Conditional jump instructions @@ -1445,13 +1357,6 @@ (pc)))] "" { - if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 - && (GET_CODE (operands[1]) == GT - || GET_CODE (operands[1]) == GE - || GET_CODE (operands[1]) == LE - || GET_CODE (operands[1]) == LT)) - return 0; - if (get_attr_length (insn) == 2) return "b%b1 %l0"; if (TARGET_V850E3V5_UP && get_attr_length (insn) == 4) @@ -1465,8 +1370,7 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 65536)) (const_int 4) - (const_int 6)))) - (set_attr "cc" "none")]) + (const_int 6))))]) (define_insn "*branch_invert" [(set (pc) @@ -1476,13 +1380,6 @@ (label_ref (match_operand 0 "" ""))))] "" { - if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0 - && (GET_CODE (operands[1]) == GT - || GET_CODE (operands[1]) == GE - || GET_CODE (operands[1]) == LE - || GET_CODE (operands[1]) == LT)) - return NULL; - if (get_attr_length (insn) == 2) return "b%B1 %l0"; @@ -1498,8 +1395,7 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 65536)) (const_int 4) - (const_int 6)))) - (set_attr "cc" "none")]) + (const_int 6))))]) (define_insn "branch_z_normal" [(set (pc) @@ -1523,8 +1419,7 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 65536)) (const_int 4) - (const_int 6)))) - (set_attr "cc" "none")]) + (const_int 6))))]) (define_insn "*branch_z_invert" [(set (pc) @@ -1548,8 +1443,7 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 65536)) (const_int 4) - (const_int 6)))) - (set_attr "cc" "none")]) + (const_int 6))))]) (define_insn "branch_nz_normal" [(set (pc) @@ -1573,8 +1467,7 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 65536)) (const_int 4) - (const_int 6)))) - (set_attr "cc" "none")]) + (const_int 6))))]) (define_insn "*branch_nz_invert" [(set (pc) @@ -1598,8 +1491,7 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 65536)) (const_int 4) - (const_int 6)))) - (set_attr "cc" "none")]) + (const_int 6))))]) ;; Unconditional and other jump instructions. @@ -1617,23 +1509,20 @@ (if_then_else (lt (abs (minus (match_dup 0) (pc))) (const_int 256)) (const_int 2) - (const_int 4))) - (set_attr "cc" "none")]) + (const_int 4)))]) (define_insn "indirect_jump" [(set (pc) (match_operand:SI 0 "register_operand" "r"))] "" "jmp %0" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) (define_insn "tablejump" [(set (pc) (match_operand:SI 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))] "" "jmp %0" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) (define_insn "switch" [(set (pc) @@ -1646,8 +1535,7 @@ (label_ref (match_dup 1))))] "(TARGET_V850E_UP)" "switch %0" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) (define_expand "casesi" [(match_operand:SI 0 "register_operand" "") @@ -1727,9 +1615,7 @@ return "jarl %0, r31"; } - [(set_attr "length" "4,8") - (set_attr "cc" "clobber,clobber")] -) + [(set_attr "length" "4,8")]) (define_insn "call_internal_long" [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r")) @@ -1753,9 +1639,7 @@ return "jarl .+4,r31 ; add 4,r31 ; jmp %0"; } - [(set_attr "length" "16,8") - (set_attr "cc" "clobber,clobber")] -) + [(set_attr "length" "16,8")]) ;; Call subroutine, returning value in operand 0 ;; (which must be a hard register). @@ -1797,9 +1681,7 @@ return "jarl %1, r31"; } - [(set_attr "length" "4,8") - (set_attr "cc" "clobber,clobber")] -) + [(set_attr "length" "4,8")]) (define_insn "call_value_internal_long" [(set (match_operand 0 "" "=r,r") @@ -1825,16 +1707,13 @@ return "jarl .+4, r31 ; add 4, r31 ; jmp %1"; } - [(set_attr "length" "16,8") - (set_attr "cc" "clobber,clobber")] -) + [(set_attr "length" "16,8")]) (define_insn "nop" [(const_int 0)] "" "nop" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) ;; ---------------------------------------------------------------------- ;; EXTEND INSTRUCTIONS @@ -1851,8 +1730,7 @@ andi 65535,%1,%0 sld.hu %1,%0 ld.hu %1,%0" - [(set_attr "length" "2,4,2,4") - (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) + [(set_attr "length" "2,4,2,4")]) (define_insn "*zero_extendhisi2_v850" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1861,8 +1739,7 @@ (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander "" "andi 65535,%1,%0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "4")]) (define_expand "zero_extendhisi2" [(parallel [(set (match_operand:SI 0 "register_operand") @@ -1886,8 +1763,7 @@ andi 255,%1,%0 sld.bu %1,%0 ld.bu %1,%0" - [(set_attr "length" "2,4,2,4") - (set_attr "cc" "none_0hit,set_zn,none_0hit,none_0hit")]) + [(set_attr "length" "2,4,2,4")]) (define_insn "*zero_extendqisi2_v850" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1896,8 +1772,7 @@ (clobber (reg:CC CC_REGNUM))] ;; A lie, but we have to match the expander "" "andi 255,%1,%0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "4")]) (define_expand "zero_extendqisi2" [(parallel [(set (match_operand:SI 0 "register_operand") @@ -1923,8 +1798,7 @@ sxh %0 sld.h %1,%0 ld.h %1,%0" - [(set_attr "length" "2,2,4") - (set_attr "cc" "none_0hit,none_0hit,none_0hit")]) + [(set_attr "length" "2,2,4")]) ;; ??? This is missing a sign extend from memory pattern to match the ld.h ;; instruction. @@ -1955,8 +1829,7 @@ sxb %0 sld.b %1,%0 ld.b %1,%0" - [(set_attr "length" "2,2,4") - (set_attr "cc" "none_0hit,none_0hit,none_0hit")]) + [(set_attr "length" "2,2,4")]) ;; ??? This is missing a sign extend from memory pattern to match the ld.b ;; instruction. @@ -1990,8 +1863,7 @@ "@ shl %2,%0 shl %2,%0" - [(set_attr "length" "4,2") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "4,2")]) (define_insn "ashlsi3_v850e2" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2001,8 +1873,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_V850E2_UP" "shl %2,%1,%0" - [(set_attr "length" "4") - (set_attr "cc" "set_znv")]) + [(set_attr "length" "4")]) (define_insn "lshrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -2014,8 +1885,7 @@ "@ shr %2,%0 shr %2,%0" - [(set_attr "length" "4,2") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "4,2")]) (define_insn "lshrsi3_v850e2" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2025,8 +1895,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_V850E2_UP" "shr %2,%1,%0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "4")]) (define_insn "ashrsi3" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -2038,8 +1907,7 @@ "@ sar %2,%0 sar %2,%0" - [(set_attr "length" "4,2") - (set_attr "cc" "set_zn, set_zn")]) + [(set_attr "length" "4,2")]) (define_insn "ashrsi3_v850e2" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2049,8 +1917,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_V850E2_UP" "sar %2,%1,%0" - [(set_attr "length" "4") - (set_attr "cc" "set_zn")]) + [(set_attr "length" "4")]) ;; ---------------------------------------------------------------------- ;; FIND FIRST BIT INSTRUCTION @@ -2062,8 +1929,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_V850E2_UP" "sch1r %1,%0" - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")]) ;; ---------------------------------------------------------------------- ;; PROLOGUE/EPILOGUE @@ -2088,16 +1954,14 @@ [(return)] "reload_completed" "jmp [r31]" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) (define_insn "return_internal" [(return) (use (reg:SI 31))] "" "jmp [r31]" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) ;; ---------------------------------------------------------------------- ;; v850e2V3 floating-point hardware support @@ -2111,7 +1975,6 @@ "TARGET_USE_FPU" "addf.s %1,%2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "adddf3" @@ -2121,7 +1984,6 @@ "TARGET_USE_FPU" "addf.d %1,%2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "subsf3" @@ -2131,7 +1993,6 @@ "TARGET_USE_FPU" "subf.s %2,%1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "subdf3" @@ -2141,7 +2002,6 @@ "TARGET_USE_FPU" "subf.d %2,%1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "mulsf3" @@ -2151,7 +2011,6 @@ "TARGET_USE_FPU" "mulf.s %1,%2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "muldf3" @@ -2161,7 +2020,6 @@ "TARGET_USE_FPU" "mulf.d %1,%2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "divsf3" @@ -2171,7 +2029,6 @@ "TARGET_USE_FPU" "divf.s %2,%1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "divdf3" @@ -2181,7 +2038,6 @@ "TARGET_USE_FPU" "divf.d %2,%1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "minsf3" @@ -2191,7 +2047,6 @@ "TARGET_USE_FPU" "minf.s %z1,%z2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "mindf3" @@ -2201,7 +2056,6 @@ "TARGET_USE_FPU" "minf.d %1,%2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "maxsf3" @@ -2211,7 +2065,6 @@ "TARGET_USE_FPU" "maxf.s %z1,%z2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "maxdf3" @@ -2221,7 +2074,6 @@ "TARGET_USE_FPU" "maxf.d %1,%2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "abssf2" @@ -2230,7 +2082,6 @@ "TARGET_USE_FPU" "absf.s %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "absdf2" @@ -2239,7 +2090,6 @@ "TARGET_USE_FPU" "absf.d %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "negsf2" @@ -2248,7 +2098,6 @@ "TARGET_USE_FPU" "negf.s %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "negdf2" @@ -2257,7 +2106,6 @@ "TARGET_USE_FPU" "negf.d %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; square-root @@ -2267,7 +2115,6 @@ "TARGET_USE_FPU" "sqrtf.s %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "sqrtdf2" @@ -2276,7 +2123,6 @@ "TARGET_USE_FPU" "sqrtf.d %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; float -> int @@ -2286,7 +2132,6 @@ "TARGET_USE_FPU" "trncf.sw %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "fixuns_truncsfsi2" @@ -2295,9 +2140,7 @@ "TARGET_USE_FPU" "trncf.suw %1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") - (set_attr "type" "fpu")] -) + (set_attr "type" "fpu")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=r") @@ -2305,7 +2148,6 @@ "TARGET_USE_FPU" "trncf.dw %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "fixuns_truncdfsi2" @@ -2314,9 +2156,7 @@ "TARGET_USE_FPU" "trncf.duw %1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") - (set_attr "type" "fpu")] -) + (set_attr "type" "fpu")]) (define_insn "fix_truncsfdi2" [(set (match_operand:DI 0 "register_operand" "=r") @@ -2324,7 +2164,6 @@ "TARGET_USE_FPU" "trncf.sl %1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "fixuns_truncsfdi2" @@ -2333,9 +2172,7 @@ "TARGET_USE_FPU" "trncf.sul %1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") - (set_attr "type" "fpu")] -) + (set_attr "type" "fpu")]) (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "register_operand" "=r") @@ -2343,7 +2180,6 @@ "TARGET_USE_FPU" "trncf.dl %1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "fixuns_truncdfdi2" @@ -2352,9 +2188,7 @@ "TARGET_USE_FPU" "trncf.dul %1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") - (set_attr "type" "fpu")] -) + (set_attr "type" "fpu")]) ;; int -> float (define_insn "floatsisf2" @@ -2363,7 +2197,6 @@ "TARGET_USE_FPU" "cvtf.ws %z1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "unsfloatsisf2" @@ -2372,7 +2205,6 @@ "TARGET_USE_FPU" "cvtf.uws %z1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "floatsidf2" @@ -2381,7 +2213,6 @@ "TARGET_USE_FPU" "cvtf.wd %z1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "unsfloatsidf2" @@ -2390,7 +2221,6 @@ "TARGET_USE_FPU" "cvtf.uwd %z1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "floatdisf2" @@ -2399,7 +2229,6 @@ "TARGET_USE_FPU" "cvtf.ls %z1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "unsfloatdisf2" @@ -2408,7 +2237,6 @@ "TARGET_USE_FPU" "cvtf.uls %z1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "floatdidf2" @@ -2417,7 +2245,6 @@ "TARGET_USE_FPU" "cvtf.ld %z1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "unsfloatdidf2" @@ -2426,7 +2253,6 @@ "TARGET_USE_FPU" "cvtf.uld %z1, %0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; single-float -> double-float @@ -2437,7 +2263,6 @@ "TARGET_USE_FPU" "cvtf.sd %z1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; double-float -> single-float @@ -2448,7 +2273,6 @@ "TARGET_USE_FPU" "cvtf.ds %1,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; @@ -2477,7 +2301,6 @@ "TARGET_USE_FPU" "recipf.s %2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_expand "recipdf2" @@ -2497,7 +2320,6 @@ "TARGET_USE_FPU" "recipf.d %2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;;; reciprocal of square-root @@ -2518,7 +2340,6 @@ "TARGET_USE_FPU" "rsqrtf.s %2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_expand "rsqrtdf2" @@ -2538,7 +2359,6 @@ "TARGET_USE_FPU" "rsqrtf.d %2,%0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; Note: The FPU-2.0 (ie pre e3v5) versions of these routines do not actually @@ -2554,7 +2374,6 @@ "TARGET_USE_FPU" { return TARGET_V850E3V5_UP ? "fmaf.s %1, %2, %0" : "maddf.s %2, %1, %3, %0"; } [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;;; multiply-subtract @@ -2566,7 +2385,6 @@ "TARGET_USE_FPU" { return TARGET_V850E3V5_UP ? "fmsf.s %1, %2, %0" : "msubf.s %2, %1, %3, %0"; } [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;;; negative-multiply-add @@ -2578,7 +2396,6 @@ "TARGET_USE_FPU" { return TARGET_V850E3V5_UP ? "fnmaf.s %1, %2, %0" : "nmaddf.s %2, %1, %3, %0"; } [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; negative-multiply-subtract @@ -2590,7 +2407,6 @@ "TARGET_USE_FPU" { return TARGET_V850E3V5_UP ? "fnmsf.s %1, %2, %0" : "nmsubf.s %2, %1, %3, %0"; } [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ; ; ---------------- comparison/conditionals @@ -2604,7 +2420,6 @@ "TARGET_USE_FPU" "cmpf.s le, %z0, %z1" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpsf_lt_insn" @@ -2614,7 +2429,6 @@ "TARGET_USE_FPU" "cmpf.s lt, %z0, %z1" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpsf_ge_insn" @@ -2624,7 +2438,6 @@ "TARGET_USE_FPU" "cmpf.s le, %z1, %z0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpsf_gt_insn" @@ -2634,7 +2447,6 @@ "TARGET_USE_FPU" "cmpf.s lt, %z1, %z0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpsf_eq_insn" @@ -2644,7 +2456,6 @@ "TARGET_USE_FPU" "cmpf.s eq, %z0, %z1" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ; DF @@ -2656,7 +2467,6 @@ "TARGET_USE_FPU" "cmpf.d le, %z0, %z1" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpdf_lt_insn" @@ -2666,7 +2476,6 @@ "TARGET_USE_FPU" "cmpf.d lt, %z0, %z1" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpdf_ge_insn" @@ -2676,7 +2485,6 @@ "TARGET_USE_FPU" "cmpf.d le, %z1, %z0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpdf_gt_insn" @@ -2686,7 +2494,6 @@ "TARGET_USE_FPU" "cmpf.d lt, %z1, %z0" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) (define_insn "cmpdf_eq_insn" @@ -2696,7 +2503,6 @@ "TARGET_USE_FPU" "cmpf.d eq, %z0, %z1" [(set_attr "length" "4") - (set_attr "cc" "none_0hit") (set_attr "type" "fpu")]) ;; @@ -2718,7 +2524,6 @@ || GET_MODE(operands[0]) == CC_FPU_NEmode)" "trfsr" [(set_attr "length" "4") - (set_attr "cc" "set_z") (set_attr "type" "fpu")]) ;; @@ -2734,8 +2539,7 @@ (match_operand:SF 1 "reg_or_0_operand" "rIG") (match_operand:SF 2 "reg_or_0_operand" "rIG")))] "TARGET_USE_FPU" - "cmovf.s 0,%z1,%z2,%0" - [(set_attr "cc" "clobber")]) ;; ??? or none_0hit + "cmovf.s 0,%z1,%z2,%0") (define_insn "movsfcc_nz_insn" [(set (match_operand:SF 0 "register_operand" "=r") @@ -2744,8 +2548,7 @@ (match_operand:SF 1 "reg_or_0_operand" "rIG") (match_operand:SF 2 "reg_or_0_operand" "rIG")))] "TARGET_USE_FPU" - "cmovf.s 0,%z2,%z1,%0" - [(set_attr "cc" "clobber")]) ;; ??? or none_0hit + "cmovf.s 0,%z2,%z1,%0") (define_insn "movdfcc_z_insn" [(set (match_operand:DF 0 "even_reg_operand" "=r") @@ -2754,8 +2557,7 @@ (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] "TARGET_USE_FPU" - "cmovf.d 0,%z1,%z2,%0" - [(set_attr "cc" "clobber")]) ;; ??? or none_0hit + "cmovf.d 0,%z1,%z2,%0") (define_insn "movdfcc_nz_insn" [(set (match_operand:DF 0 "even_reg_operand" "=r") @@ -2764,8 +2566,7 @@ (match_operand:DF 1 "even_reg_operand" "r") (match_operand:DF 2 "even_reg_operand" "r")))] "TARGET_USE_FPU" - "cmovf.d 0,%z2,%z1,%0" - [(set_attr "cc" "clobber")]) ;; ??? or none_0hit + "cmovf.d 0,%z2,%z1,%0") (define_insn "movedfcc_z_zero" [(set (match_operand:DF 0 "register_operand" "=r") @@ -2775,8 +2576,7 @@ (match_operand:DF 2 "reg_or_0_operand" "rIG")))] "TARGET_USE_FPU" "cmovf.s 0,%z1,%z2,%0 ; cmovf.s 0,%Z1,%Z2,%R0" - [(set_attr "length" "8") - (set_attr "cc" "clobber")]) ;; ??? or none_0hit + [(set_attr "length" "8")]) (define_insn "movedfcc_nz_zero" [(set (match_operand:DF 0 "register_operand" "=r") @@ -2786,8 +2586,7 @@ (match_operand:DF 2 "reg_or_0_operand" "rIG")))] "TARGET_USE_FPU" "cmovf.s 0,%z2,%z1,%0 ; cmovf.s 0,%Z2,%Z1,%R0" - [(set_attr "length" "8") - (set_attr "cc" "clobber")]) ;; ??? or none_0hit + [(set_attr "length" "8")]) ;; ---------------------------------------------------------------------- @@ -2813,8 +2612,7 @@ { return construct_prepare_instruction (operands[0]); } - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")]) (define_insn "" [(match_parallel 0 "pattern_is_ok_for_prologue" @@ -2829,8 +2627,7 @@ } [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") (const_string "16") - (const_string "4"))) - (set_attr "cc" "clobber")]) + (const_string "4")))]) ;; ;; Actually, turn the RTXs into a DISPOSE instruction. @@ -2847,8 +2644,7 @@ { return construct_dispose_instruction (operands[0]); } - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")]) ;; This pattern will match a return RTX followed by any number of pop RTXs ;; and possible a stack adjustment as well. These RTXs will be turned into @@ -2868,8 +2664,7 @@ } [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes") (const_string "12") - (const_string "4"))) - (set_attr "cc" "clobber")]) + (const_string "4")))]) ;; Initialize an interrupt function. Do not depend on TARGET_PROLOG_FUNCTION. (define_insn "callt_save_interrupt" @@ -2891,15 +2686,13 @@ output_asm_insn ("callt ctoff(__callt_save_interrupt)", operands); return ""; } - [(set_attr "length" "26") - (set_attr "cc" "clobber")]) + [(set_attr "length" "26")]) (define_insn "callt_return_interrupt" [(unspec_volatile [(const_int 0)] 3)] "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT" "callt ctoff(__callt_return_interrupt)" - [(set_attr "length" "2") - (set_attr "cc" "clobber")]) + [(set_attr "length" "2")]) (define_insn "save_interrupt" [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -20))) @@ -2930,8 +2723,7 @@ [(set (attr "length") (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 10) - (const_int 34))) - (set_attr "cc" "clobber")]) + (const_int 34)))]) ;; Restore r1, r4, r10, and return from the interrupt (define_insn "return_interrupt" @@ -2961,8 +2753,7 @@ [(set (attr "length") (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 4) - (const_int 24))) - (set_attr "cc" "clobber")]) + (const_int 24)))]) ;; Save all registers except for the registers saved in save_interrupt when ;; an interrupt function makes a call. @@ -2975,8 +2766,7 @@ [(unspec_volatile [(const_int 0)] 0)] "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT" "callt ctoff(__callt_save_all_interrupt)" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) (define_insn "save_all_interrupt" [(unspec_volatile [(const_int 0)] 0)] @@ -3054,16 +2844,13 @@ [(set (attr "length") (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 4) - (const_int 62) - )) - (set_attr "cc" "clobber")]) + (const_int 62)))]) (define_insn "_save_all_interrupt" [(unspec_volatile [(const_int 0)] 0)] "TARGET_V850 && ! TARGET_LONG_CALLS" "jarl __save_all_interrupt,r10" - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")]) ;; Restore all registers saved when an interrupt function makes a call. ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and @@ -3075,8 +2862,7 @@ [(unspec_volatile [(const_int 0)] 1)] "(TARGET_V850E_UP) && !TARGET_DISABLE_CALLT" "callt ctoff(__callt_restore_all_interrupt)" - [(set_attr "length" "2") - (set_attr "cc" "none")]) + [(set_attr "length" "2")]) (define_insn "restore_all_interrupt" [(unspec_volatile [(const_int 0)] 1)] @@ -3153,12 +2939,10 @@ (if_then_else (match_test "TARGET_LONG_CALLS") (const_int 4) (const_int 62) - )) - (set_attr "cc" "clobber")]) + ))]) (define_insn "_restore_all_interrupt" [(unspec_volatile [(const_int 0)] 1)] "TARGET_V850 && ! TARGET_LONG_CALLS" "jarl __restore_all_interrupt,r10" - [(set_attr "length" "4") - (set_attr "cc" "clobber")]) + [(set_attr "length" "4")])