From: Luke Kenneth Casson Leighton Date: Fri, 16 Oct 2020 18:26:05 +0000 (+0100) Subject: set defaults in pspec X-Git-Tag: 24jan2021_ls180~140 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03e33b06a77448f40b3e46fb1a5e178ddb7472b6;p=soc.git set defaults in pspec --- diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 3d1359ea..012e5b19 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -147,6 +147,10 @@ class TestRunner(FHDLTestCase): mask_wid=8, imem_reg_wid=64, #wb_data_width=32, + use_pll=False, + nocore=False, + xics=False, + gpio=False, reg_wid=64) m.submodules.issuer = issuer = TestIssuerInternal(pspec) imem = issuer.imem._get_memory() @@ -307,13 +311,13 @@ if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() # suite.addTest(TestRunner(HelloTestCases.test_data)) - suite.addTest(TestRunner(DivTestCases().test_data)) + #suite.addTest(TestRunner(DivTestCases().test_data)) # suite.addTest(TestRunner(AttnTestCase.test_data)) - suite.addTest(TestRunner(GeneralTestCases.test_data)) - suite.addTest(TestRunner(LDSTTestCase().test_data)) - suite.addTest(TestRunner(CRTestCase().test_data)) - suite.addTest(TestRunner(ShiftRotTestCase().test_data)) - suite.addTest(TestRunner(LogicalTestCase().test_data)) + #suite.addTest(TestRunner(GeneralTestCases.test_data)) + #suite.addTest(TestRunner(LDSTTestCase().test_data)) + #suite.addTest(TestRunner(CRTestCase().test_data)) + #suite.addTest(TestRunner(ShiftRotTestCase().test_data)) + #suite.addTest(TestRunner(LogicalTestCase().test_data)) suite.addTest(TestRunner(ALUTestCase().test_data)) # suite.addTest(TestRunner(BranchTestCase.test_data)) # suite.addTest(TestRunner(SPRTestCase.test_data))