From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Feb 2014 13:25:29 +0000 (+0100)
Subject: Added support for "keep" attribute to abc pass
X-Git-Tag: yosys-0.2.0~41
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03ee63ff80dae4eefc463975f183b501a1f98c95;p=yosys.git

Added support for "keep" attribute to abc pass
---

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 8f873867d..5aa13572e 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -447,7 +447,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 		extract_cell(c);
 
 	for (auto &wire_it : module->wires) {
-		if (wire_it.second->port_id > 0)
+		if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep"))
 			mark_port(RTLIL::SigSpec(wire_it.second));
 	}