From: Paul Mackerras <paulus@ozlabs.org>
Date: Thu, 11 Jun 2020 04:57:30 +0000 (+1000)
Subject: tests/xics: Fix assumption that interrupts happen immediately
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03f9d7a97e8bbec46b2cbd3386774295e48a8387;p=microwatt.git

tests/xics: Fix assumption that interrupts happen immediately

Currently the test writes to the XICS and then checks that the
expected interrupt has happened.  This turns into a stbcix
instruction followed immediately by a load from the variable that
indicates whether an interrupt has happened.  It is possible for
it to take a few cycles for the store to reach the XICS and the
interrupt request signal to come back to the core, particularly
with improvements to the load/store unit and dcache.

This therefore adds a delay between storing to the XICS and
checking for the occurrence of an interrupt, so as to give the
signals time to propagate.  The delay loop does an arbitrary 10
iterations, and each iteration does two loads and one store to
(cacheable) memory.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---

diff --git a/tests/test_xics.bin b/tests/test_xics.bin
index 6dd993c..327f98f 100755
Binary files a/tests/test_xics.bin and b/tests/test_xics.bin differ
diff --git a/tests/xics/xics.c b/tests/xics/xics.c
index 2ff4c54..a2db3a5 100644
--- a/tests/xics/xics.c
+++ b/tests/xics/xics.c
@@ -9,6 +9,14 @@
 #undef DEBUG
 //#define DEBUG 1
 
+void delay(void)
+{
+	static volatile int i;
+
+	for (i = 0; i < 10; ++i)
+		;
+}
+
 void print_number(unsigned int i) // only for i = 0-999
 {
 	unsigned int j, k, m;
@@ -148,14 +156,17 @@ int xics_test_0(void)
 	xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt
 
 	// still masked, so shouldn't happen yet
+	delay();
 	assert(isrs_run == 0);
 
 	// unmask IPI only
 	xics_write8(XICS_XIRR, 0x40);
+	delay();
 	assert(isrs_run == ISR_IPI);
 
 	// unmask UART
 	xics_write8(XICS_XIRR, 0xc0);
+	delay();
 	assert(isrs_run == (ISR_IPI | ISR_UART));
 
 	// cleanup
@@ -174,12 +185,14 @@ int xics_test_1(void)
 	xics_write8(XICS_XIRR, 0xff); // allow all interrupts
 
 	// should be none pending
+	delay();
 	assert(isrs_run == 0);
 
 	// trigger both
 	potato_uart_irq_en(); // cause 0x500 interrupt
 	xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt
 
+	delay();
 	assert(isrs_run == (ISR_IPI | ISR_UART));
 
 	// cleanup
@@ -208,9 +221,11 @@ int xics_test_2(void)
 	// trigger an IPI
 	xics_write8(XICS_MFRR, 0x05); // cause 0x500 interrupt
 
+	delay();
 	assert(isrs_run == 0);
 
 	mtmsrd(0x9000000000008003); // EE on
+	delay();
 	assert(isrs_run == ISR_IPI);
 
 	// cleanup