From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 12 Feb 2021 15:07:09 +0000 (+0000)
Subject: add skip of instruction if SVSTATE.VL=0 in ISACaller
X-Git-Tag: convert-csv-opcode-to-binary~240
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=03fb36fabbc8e9142f5f155055e466f30d19f95e;p=soc.git

add skip of instruction if SVSTATE.VL=0 in ISACaller
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 4a38a1ed..03bf16d2 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -869,6 +869,14 @@ class ISACaller:
 
         # get SVSTATE srcstep.  TODO: dststep (twin predication)
         srcstep = self.svstate.srcstep.asint(msb0=True)
+        vl = self.svstate.vl.asint(msb0=True)
+        mvl = self.svstate.maxvl.asint(msb0=True)
+
+        # VL=0 in SVP64 mode means "do nothing: skip instruction"
+        if self.is_svp64_mode and vl == 0:
+            self.pc.update(self.namespace, self.is_svp64_mode)
+            print("end of call", self.namespace['CIA'], self.namespace['NIA'])
+            return
 
         # main input registers (RT, RA ...)
         inputs = []