From: Luke Kenneth Casson Leighton Date: Thu, 22 Apr 2021 15:31:23 +0000 (+0100) Subject: r1.end_row_ix off-by-one in dcache X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=040969376f20fe548fb7f6175bc3e30bc23ad492;p=soc.git r1.end_row_ix off-by-one in dcache --- diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 61fd1071..5d7d8451 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1241,8 +1241,7 @@ class DCache(Elaboratable): # complete tlbies and TLB loads in the third cycle sync += r1.mmu_done.eq(r0_valid & (r0.tlbie | r0.tlbld)) - with m.If((req_op == Op.OP_LOAD_HIT) - | (req_op == Op.OP_STCX_FAIL)): + with m.If((req_op == Op.OP_LOAD_HIT) | (req_op == Op.OP_STCX_FAIL)): with m.If(~r0.mmu_req): sync += r1.ls_valid.eq(1) with m.Else(): @@ -1307,7 +1306,7 @@ class DCache(Elaboratable): # for subsequent stores. sync += r1.store_index.eq(req_idx) sync += r1.store_row.eq(req_row) - sync += r1.end_row_ix.eq(get_row_of_line(req_row)) + sync += r1.end_row_ix.eq(get_row_of_line(req_row)-1) sync += r1.reload_tag.eq(req_tag) sync += r1.req.same_tag.eq(1)