From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Thu, 28 Jul 2022 13:49:21 +0000 (+0300)
Subject: ppc/svp64: share SVP64 context via libopcodes
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0411c9c2e1a64efd87c0151de3bf15400ab5ef80;p=binutils-gdb.git

ppc/svp64: share SVP64 context via libopcodes
---

diff --git a/gas/config/tc-ppc-svp64.c b/gas/config/tc-ppc-svp64.c
index ec0fda793c8..a02815f9e33 100644
--- a/gas/config/tc-ppc-svp64.c
+++ b/gas/config/tc-ppc-svp64.c
@@ -21,49 +21,6 @@
 
 #include <setjmp.h>
 
-struct svp64_ctx {
-  const struct svp64_desc *desc;
-  struct svp64_insn insn;
-  unsigned int pmmode : 1;
-  unsigned int pmask : 3;
-  unsigned int smmode : 1;
-  unsigned int smask : 3;
-  unsigned int mmode : 1;
-  unsigned int has_pmask : 1;
-  unsigned int has_smask : 1;
-  unsigned int mask_m_specified : 1;
-  unsigned int subvl : 2;
-  unsigned int destwid : 2;
-  unsigned int srcwid : 2;
-  unsigned int ldst_elstride : 1;
-  unsigned int sv_mode_explicit : 1;
-  unsigned int sv_mode : 2;
-  unsigned int sat : 1;
-  unsigned int src_zero : 1;
-  unsigned int dst_zero : 1;
-  unsigned int ff : 3 + 2; /* 3-bit plus RC1 */
-  unsigned int pr : 3 + 2; /* 3-bit plus RC1 */
-  unsigned int mr : 1;
-  unsigned int rg : 1;
-  unsigned int crm : 1;
-  unsigned int type : 2;
-  unsigned int rc : 1;
-  unsigned int mode : 5;
-
-  /* These are not implemented yet. */
-  unsigned int bc_all : 1;
-  unsigned int bc_lru : 1;
-  unsigned int bc_brc : 1;
-  unsigned int bc_svstep : 1;
-  unsigned int bc_vsb : 1;
-  unsigned int bc_vlset : 1;
-  unsigned int bc_vli : 1;
-  unsigned int bc_snz : 1;
-};
-
-#define SVP64_RC1_ACTIVE (1U << 3U)
-#define SVP64_RC1_INVERT (SVP64_RC1_ACTIVE | (1U << 4U))
-
 enum svp64_type {
   SVP64_TYPE_NONE,
   SVP64_TYPE_LD,
diff --git a/include/opcode/ppc-svp64.h b/include/opcode/ppc-svp64.h
index 87cac813436..b37024212a7 100644
--- a/include/opcode/ppc-svp64.h
+++ b/include/opcode/ppc-svp64.h
@@ -37,6 +37,49 @@ struct svp64_extra_desc {
 const struct svp64_extra_desc *
 svp64_extra_desc (const struct svp64_desc *desc, ppc_opindex_t opindex);
 
+struct svp64_ctx {
+  const struct svp64_desc *desc;
+  struct svp64_insn insn;
+  unsigned int pmmode : 1;
+  unsigned int pmask : 3;
+  unsigned int smmode : 1;
+  unsigned int smask : 3;
+  unsigned int mmode : 1;
+  unsigned int has_pmask : 1;
+  unsigned int has_smask : 1;
+  unsigned int mask_m_specified : 1;
+  unsigned int subvl : 2;
+  unsigned int destwid : 2;
+  unsigned int srcwid : 2;
+  unsigned int ldst_elstride : 1;
+  unsigned int sv_mode_explicit : 1;
+  unsigned int sv_mode : 2;
+  unsigned int sat : 1;
+  unsigned int src_zero : 1;
+  unsigned int dst_zero : 1;
+  unsigned int ff : 3 + 2; /* 3-bit plus RC1 */
+  unsigned int pr : 3 + 2; /* 3-bit plus RC1 */
+  unsigned int mr : 1;
+  unsigned int rg : 1;
+  unsigned int crm : 1;
+  unsigned int type : 2;
+  unsigned int rc : 1;
+  unsigned int mode : 5;
+
+  /* These are not implemented yet. */
+  unsigned int bc_all : 1;
+  unsigned int bc_lru : 1;
+  unsigned int bc_brc : 1;
+  unsigned int bc_svstep : 1;
+  unsigned int bc_vsb : 1;
+  unsigned int bc_vlset : 1;
+  unsigned int bc_vli : 1;
+  unsigned int bc_snz : 1;
+};
+
+#define SVP64_RC1_ACTIVE (1U << 3U)
+#define SVP64_RC1_INVERT (SVP64_RC1_ACTIVE | (1U << 4U))
+
 #ifdef __cplusplus
 }
 #endif