From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 10 Sep 2019 23:14:26 +0000 (-0700)
Subject: Update CHANGELOG
X-Git-Tag: working-ls180~1039^2~147
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04153c501128ae37c7ed1235266ab6b32902b878;p=yosys.git

Update CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index c29429295..f0a0d0fae 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -38,6 +38,11 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Improvements in pmgen: slices, choices, define, generate
     - Added "xilinx_srl" for Xilinx shift register extraction
     - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
+    - Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+    - Added "xilinx_dsp" for Xilinx DSP packing
+    - "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
+    - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
+    - "synth_ice40 -dsp" to infer DSP blocks
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------