From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 May 2020 17:48:27 +0000 (+0100)
Subject: comment output stage
X-Git-Tag: div_pipeline~1303
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=042dcda38e738d030161d23210a1286e347b20d4;p=soc.git

comment output stage
---

diff --git a/src/soc/alu/output_stage.py b/src/soc/alu/output_stage.py
index 59061222..14953ca3 100644
--- a/src/soc/alu/output_stage.py
+++ b/src/soc/alu/output_stage.py
@@ -22,14 +22,14 @@ class ALUOutputStage(PipeModBase):
         m = Module()
         comb = m.d.comb
 
+        # op requests inversion of the output
         o = Signal.like(self.i.o)
         with m.If(self.i.ctx.op.invert_out):
             comb += o.eq(~self.i.o)
         with m.Else():
             comb += o.eq(self.i.o)
-        
-
 
+        # create condition register cr0 and sticky-overflow
         is_zero = Signal(reset_less=True)
         is_positive = Signal(reset_less=True)
         is_negative = Signal(reset_less=True)