From: lkcl <lkcl@web>
Date: Thu, 9 Jun 2022 09:31:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1903
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0447a510ab285d1854903505621b44769af55e7e;p=libreriscv.git

---

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index f029c08a6..8ab3f5f55 100644
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -80,9 +80,25 @@ a 5x4 result:
     svremap 31, 1, 2, 3, 0, 0, 0, 0
     sv.fmadds 0.v, 8.v, 16.v, 0.v
 
-The example may be executed as a unit test and demo,
+* svshape sets up the four SVSHAPE SPRS
+* svremap activates all five registers RA RB RC RT RS (31)
+* svremap requests:
+  - RA to use SVSHAPE1
+  - RB to use SVSHAPE2
+  - RC to use SVSHAPE3
+  - RT to use SVSHAPE0
+  - RS to use SVSHAPE0
+* sv.fmadds has RT=0.v, RA=8.v, RB=16.v, RC=0.v
+* With REMAP being active each register's element index is
+  *independently* transformed using the specified SHAPEs.
+
+Thus the Vector Loop is arranged such that the use of
+the multiply-and-accumulate instruction executes precisely the required
+Schedule to perform an in-place in-registers Matrix Multiply with no
+need to perform additional Transpose or register copy instructions.
+The example above may be executed as a unit test and demo,
 [here](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;h=c15479db9a36055166b6b023c7495f9ca3637333;hb=a17a252e474d5d5bf34026c25a19682e3f2015c3#l94)
-
+     
 # REMAP types
 
 This section summarises the motivation for each REMAP Schedule