From: Jason Ekstrand Date: Sat, 18 Nov 2017 00:10:53 +0000 (-0800) Subject: i965/miptree: Add an explicit tiling parameter to create_for_bo X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0465dd13d26451e2a57684d1ca6329dfbdeac9f4;p=mesa.git i965/miptree: Add an explicit tiling parameter to create_for_bo Otherwise, create_for_bo will just grab the tiling from the BO which is not what we want when using modifiers. Reviewed-by: Kenneth Graunke Cc: mesa-stable@lists.freedesktop.org --- diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 680121b6ab1..56700d761f4 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -934,7 +934,8 @@ brw_blorp_upload_miptree(struct brw_context *brw, brw, src_bo, src_format, src_offset + i * src_image_stride, width, height, 1, - src_row_stride, 0); + src_row_stride, + ISL_TILING_LINEAR, 0); if (!src_mt) { perf_debug("intel_texsubimage: miptree creation for src failed\n"); @@ -1055,7 +1056,8 @@ brw_blorp_download_miptree(struct brw_context *brw, brw, dst_bo, dst_format, dst_offset + i * dst_image_stride, width, height, 1, - dst_row_stride, 0); + dst_row_stride, + ISL_TILING_LINEAR, 0); if (!dst_mt) { perf_debug("intel_texsubimage: miptree creation for src failed\n"); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index c30eae420cd..296335040dc 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -1564,6 +1564,9 @@ intel_process_dri2_buffer(struct brw_context *brw, return; } + uint32_t tiling, swizzle; + brw_bo_get_tiling(bo, &tiling, &swizzle); + struct intel_mipmap_tree *mt = intel_miptree_create_for_bo(brw, bo, @@ -1573,6 +1576,7 @@ intel_process_dri2_buffer(struct brw_context *brw, drawable->h, 1, buffer->pitch, + isl_tiling_from_i915_tiling(tiling), MIPTREE_CREATE_DEFAULT); if (!mt) { brw_bo_unreference(bo); diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index b56a51e6f67..fd506163e95 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -804,11 +804,11 @@ intel_miptree_create_for_bo(struct brw_context *brw, uint32_t height, uint32_t depth, int pitch, + enum isl_tiling tiling, enum intel_miptree_create_flags flags) { const struct gen_device_info *devinfo = &brw->screen->devinfo; struct intel_mipmap_tree *mt; - uint32_t tiling, swizzle; const GLenum target = depth > 1 ? GL_TEXTURE_2D_ARRAY : GL_TEXTURE_2D; const GLenum base_format = _mesa_get_format_base_format(format); @@ -846,12 +846,10 @@ intel_miptree_create_for_bo(struct brw_context *brw, return mt; } - brw_bo_get_tiling(bo, &tiling, &swizzle); - /* Nothing will be able to use this miptree with the BO if the offset isn't * aligned. */ - if (tiling != I915_TILING_NONE) + if (tiling != ISL_TILING_LINEAR) assert(offset % 4096 == 0); /* miptrees can't handle negative pitch. If you need flipping of images, @@ -866,7 +864,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, mt = make_surface(brw, target, format, 0, 0, width, height, depth, 1, - 1lu << isl_tiling_from_i915_tiling(tiling), + 1lu << tiling, ISL_SURF_USAGE_RENDER_TARGET_BIT | ISL_SURF_USAGE_TEXTURE_BIT, 0, pitch, bo); @@ -891,7 +889,8 @@ intel_miptree_create_for_bo(struct brw_context *brw, static struct intel_mipmap_tree * miptree_create_for_planar_image(struct brw_context *brw, - __DRIimage *image, GLenum target) + __DRIimage *image, GLenum target, + enum isl_tiling tiling) { const struct intel_image_format *f = image->planar_format; struct intel_mipmap_tree *planar_mt = NULL; @@ -913,6 +912,7 @@ miptree_create_for_planar_image(struct brw_context *brw, image->offsets[index], width, height, 1, image->strides[index], + tiling, MIPTREE_CREATE_NO_AUX); if (mt == NULL) return NULL; @@ -987,8 +987,13 @@ intel_miptree_create_for_dri_image(struct brw_context *brw, mesa_format format, bool is_winsys_image) { + uint32_t bo_tiling, bo_swizzle; + brw_bo_get_tiling(image->bo, &bo_tiling, &bo_swizzle); + + const enum isl_tiling tiling = isl_tiling_from_i915_tiling(bo_tiling); + if (image->planar_format && image->planar_format->nplanes > 1) - return miptree_create_for_planar_image(brw, image, target); + return miptree_create_for_planar_image(brw, image, target, tiling); if (image->planar_format) assert(image->planar_format->planes[0].dri_format == image->dri_format); @@ -1037,7 +1042,7 @@ intel_miptree_create_for_dri_image(struct brw_context *brw, struct intel_mipmap_tree *mt = intel_miptree_create_for_bo(brw, image->bo, format, image->offset, image->width, image->height, 1, - image->pitch, mt_create_flags); + image->pitch, tiling, mt_create_flags); if (mt == NULL) return NULL; diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 5b7d7ef4f71..c3f1bfea5b5 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -401,6 +401,7 @@ intel_miptree_create_for_bo(struct brw_context *brw, uint32_t height, uint32_t depth, int pitch, + enum isl_tiling tiling, enum intel_miptree_create_flags flags); struct intel_mipmap_tree * diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c b/src/mesa/drivers/dri/i965/intel_pixel_draw.c index 81299da3295..e72c8babc81 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c @@ -118,6 +118,7 @@ do_blit_drawpixels(struct gl_context * ctx, src_offset, width, height, 1, src_stride, + ISL_TILING_LINEAR, MIPTREE_CREATE_DEFAULT); if (!pbo_mt) return false; diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 2ee36583c46..90b65196257 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -488,6 +488,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, rb->Base.Base.Width, rb->Base.Base.Height, 1, rb->mt->surf.row_pitch, + rb->mt->surf.tiling, MIPTREE_CREATE_DEFAULT); if (mt == NULL) return;