From: lkcl <lkcl@web>
Date: Thu, 28 Jan 2021 23:27:20 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~262
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0467d5fa2edf538844d4a5dcb777154dfb1e7ddb;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index d0b5b87ae..1b430165a 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -71,6 +71,10 @@ An autogenerator containing CSV files is available so that the task of creating
 * python-based assembler-translator: 40% done (lkcl)
 * c++ macros: underway (jacob)
 
+Links:
+
+* <https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv_analysis.py;hb=HEAD>
+
 ## SVSTATE SPR needed
 
 This is a peer of MSR but is stored in an SPR.  It should be considered part of the state of PC+MSR because SVSTATE is effectively a Sub-PC.