From: Staf Verhaegen <staf@stafverhaegen.be>
Date: Fri, 4 Jun 2021 09:28:47 +0000 (+0200)
Subject: Use cocotb test on ls180/experiments9 with reconnected clock.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=046b6651bf3543b6ae483832e25ea5010dfaf7ee;p=soc-cocotb-sim.git

Use cocotb test on ls180/experiments9 with reconnected clock.
---

diff --git a/ls180/experiment9_recon/.gitignore b/ls180/experiment9_recon/.gitignore
new file mode 100644
index 0000000..9b4246b
--- /dev/null
+++ b/ls180/experiment9_recon/.gitignore
@@ -0,0 +1 @@
+mem*.init
diff --git a/ls180/experiment9_recon/Makefile b/ls180/experiment9_recon/Makefile
new file mode 100644
index 0000000..68efc45
--- /dev/null
+++ b/ls180/experiment9_recon/Makefile
@@ -0,0 +1,18 @@
+ifeq ($(SIM),)
+  $(error Use one of the run_*.sh scripts to run cocotb test bench)
+endif
+
+TOPLEVEL_LANG := verilog
+
+# within soc repo, as submodule, this works after "make ls180"
+# is run inside the litex/florent subdirectory
+VERILOG_SOURCES := \
+  ../spblock_512w64b8w.v \
+  ../pll.v \
+  full_core_4_4ksram_libresoc_recon.v \
+  full_core_4_4ksram_litex_ls180_recon.v \
+# END VERILOG_SOURCES
+
+MODULE := test
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/ls180/experiment9_recon/idcode.svf b/ls180/experiment9_recon/idcode.svf
new file mode 120000
index 0000000..2a25c9b
--- /dev/null
+++ b/ls180/experiment9_recon/idcode.svf
@@ -0,0 +1 @@
+../pre_pnr/idcode.svf
\ No newline at end of file
diff --git a/ls180/experiment9_recon/run_iverilog_ls180.sh b/ls180/experiment9_recon/run_iverilog_ls180.sh
new file mode 100755
index 0000000..eae0986
--- /dev/null
+++ b/ls180/experiment9_recon/run_iverilog_ls180.sh
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+touch mem.init mem_1.init mem_2.init mem_3.init mem_4.init
+# Only run test in reset state as running CPU takes too much time to simulate
+make \
+  SIM=icarus \
+  TOPLEVEL=ls180 \
+  COCOTB_RESULTS_FILE=results_iverilog_ls180.xml \
+  COCOTB_HDL_TIMEUNIT=100ps \
+  TESTCASE="idcode_reset,idcodesvf_reset,boundary_scan_reset" \
+  SIM_BUILD=sim_build_iverilog_ls180
+
+
diff --git a/ls180/experiment9_recon/test.py b/ls180/experiment9_recon/test.py
new file mode 120000
index 0000000..252c03e
--- /dev/null
+++ b/ls180/experiment9_recon/test.py
@@ -0,0 +1 @@
+../pre_pnr/test.py
\ No newline at end of file
diff --git a/ls180/pll.v b/ls180/pll.v
new file mode 100644
index 0000000..d26cf79
--- /dev/null
+++ b/ls180/pll.v
@@ -0,0 +1,15 @@
+// PLL simulation model; just connect input clock to output clock
+module pll(ref_v, div_out_test, a0, a1, vco_test_ana, out_v);
+  input a0;
+  input a1;
+  output div_out_test;
+  output out_v;
+  input ref_v;
+  output vco_test_ana;
+
+assign out_v = ref_v;
+assign vco_test_ana = 0;
+assign div_out_test = 0;
+
+endmodule
+
diff --git a/ls180/spblock_512w64b8w.v b/ls180/spblock_512w64b8w.v
new file mode 100644
index 0000000..7fe1bda
--- /dev/null
+++ b/ls180/spblock_512w64b8w.v
@@ -0,0 +1,35 @@
+// SPBlock_512W64B8W simulation mode
+module spblock_512w64b8w(
+    input clk,
+    input [8:0] a,
+    input [63:0] d,
+    output [63:0] q,
+    // Width of WE determines the write granularity
+    input [7:0] we
+);
+
+genvar i;
+
+reg [63:0] ram [511:0];
+wire[7:0] d_split [7:0];
+reg [8:0] a_hold;
+
+always @(posedge clk) begin
+    a_hold <= a;
+end
+
+assign q = ram[a_hold];
+
+generate
+    for (i = 0; i < 8; i = i + 1) begin
+        assign d_split[i] = d[((i + 1)*8 - 1):i*8];
+
+        always @(posedge clk) begin
+            if (we[i]) begin
+                ram[a][((i + 1)*8 - 1):i*8] = d_split[i];
+            end
+        end
+    end
+endgenerate
+
+endmodule