From: Kevin Lim <ktlim@umich.edu>
Date: Fri, 23 Mar 2007 17:20:19 +0000 (-0400)
Subject: Merge ktlim@zizzer:/bk/newmem
X-Git-Tag: m5_2.0_beta3~74
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=047f77102b5e5d63549663ee94cd799cdcf63516;p=gem5.git

Merge ktlim@zizzer:/bk/newmem
into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
    Hand merge.  Line is no longer needed because it's handled in the ISA.

--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
---

047f77102b5e5d63549663ee94cd799cdcf63516
diff --cc src/cpu/o3/cpu.cc
index 38e6a0b5b,f9e094d75..354e3c490
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@@ -983,7 -977,26 +983,7 @@@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *
          }
      }
      if (!tickEvent.scheduled())
-         tickEvent.schedule(curTick);
+         tickEvent.schedule(nextCycle());
 -
 -    Port *peer;
 -    Port *icachePort = fetch.getIcachePort();
 -    if (icachePort->getPeer() == NULL) {
 -        peer = oldCPU->getPort("icache_port")->getPeer();
 -        icachePort->setPeer(peer);
 -    } else {
 -        peer = icachePort->getPeer();
 -    }
 -    peer->setPeer(icachePort);
 -
 -    Port *dcachePort = iew.getDcachePort();
 -    if (dcachePort->getPeer() == NULL) {
 -        peer = oldCPU->getPort("dcache_port")->getPeer();
 -        dcachePort->setPeer(peer);
 -    } else {
 -        peer = dcachePort->getPeer();
 -    }
 -    peer->setPeer(dcachePort);
  }
  
  template <class Impl>
diff --cc src/mem/cache/miss/miss_queue.cc
index 25b8fcbeb,38c5ffa71..24ca9cfa2
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@@ -596,9 -601,10 +596,10 @@@ MissQueue::handleResponse(PacketPtr &pk
  
          if (mshr->hasTargets()) {
              // Didn't satisfy all the targets, need to resend
 -            Packet::Command cmd = mshr->getTarget()->cmd;
 +            MemCmd cmd = mshr->getTarget()->cmd;
              mshr->pkt->setDest(Packet::Broadcast);
              mshr->pkt->result = Packet::Unknown;
+             mshr->pkt->req = mshr->getTarget()->req;
              mq.markPending(mshr, cmd);
              mshr->order = order++;
              cache->setMasterRequest(Request_MSHR, time);