From: David Shah <dave@ds0.me>
Date: Fri, 22 Nov 2019 15:32:46 +0000 (+0000)
Subject: Update CHANGELOG and README
X-Git-Tag: working-ls180~824^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0488492ad269df9641ab317eac5568353dd61076;p=yosys.git

Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/CHANGELOG b/CHANGELOG
index 481ba266e..241fba9e8 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -55,6 +55,7 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "check -mapped"
     - Added checking of SystemVerilog always block types (always_comb,
       always_latch and always_ff)
+    - Added support for SystemVerilog wildcard port connections (.*)
     - Added "xilinx_dffopt" pass
     - Added "scratchpad" pass
     - Added "abc9 -dff"
diff --git a/README.md b/README.md
index 77e9410da..327d407f9 100644
--- a/README.md
+++ b/README.md
@@ -387,6 +387,10 @@ Verilog Attributes and non-standard features
   according to the type of the always. These are checked for correctness in
   ``proc_dlatch``.
 
+- The cell attribute ``wildcard_port_conns`` represents wildcard port
+  connections (SystemVerilog ``.*``). These are resolved to concrete
+  connections to matching wires in ``hierarchy``.  
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset