From: programmerjake <programmerjake@web>
Date: Wed, 21 Sep 2022 21:45:09 +0000 (+0100)
Subject: fix spelling
X-Git-Tag: opf_rfc_ls005_v1~336
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=048bd61319a48f3bf9bee1f73345d0f3779a82ed;p=libreriscv.git

fix spelling
---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 6fc55599f..0523ed040 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -201,7 +201,7 @@ and irrevocably causes binary non-interoperability *despite being
 a "feature"*.  Explained in <https://m.youtube.com/watch?v=HNEm8zmkjBU>
 it is the exact same binary-incompatibility issue faced by Power ISA
 on its 32- to 64-bit transition: 32-bit hardware was **unable** to
-trap-and-emulate 64-bit binarues because the opcodes were (are) the same.
+trap-and-emulate 64-bit binaries because the opcodes were (are) the same.
 
 It is therefore *guaranteed* that extensions to the register file
 width and quantity in Simple-V shall only be made in future by