From: Francisco Jerez Date: Sun, 5 Jan 2020 00:11:23 +0000 (-0800) Subject: intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04c7d3d4b19610cae8250102fefd0012b7233d9e;p=mesa.git intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders. In SIMD32 programs that don't use discard, the upper 16 bits of the UD result of sample_mask_reg() don't contain the sample mask of the upper 16 channels as one would expect. Stop pretending we are returning a valid 32-bit mask. Reviewed-by: Kenneth Graunke --- diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index b19d9b3e8cb..963d1c18155 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4290,7 +4290,7 @@ sample_mask_reg(const fs_builder &bld) } else { assert(v->devinfo->gen >= 6 && bld.dispatch_width() <= 16); return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7), - BRW_REGISTER_TYPE_UD); + BRW_REGISTER_TYPE_UW); } } @@ -5337,8 +5337,7 @@ emit_predicate_on_sample_mask(const fs_builder &bld, fs_inst *inst) subreg + inst->group / 16).subnr); } else { bld.group(1, 0).exec_all() - .MOV(brw_flag_subreg(subreg + inst->group / 16), - retype(sample_mask, BRW_REGISTER_TYPE_UW)); + .MOV(brw_flag_subreg(subreg + inst->group / 16), sample_mask); } if (inst->predicate) {