From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 12 Sep 2022 21:36:29 +0000 (+0100)
Subject: add hack overloaded meaning of destwid to be pack/unpack.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04d0ba9a29869a06becd424de6184fc95dfc643d;p=openpower-isa.git

add hack overloaded meaning of destwid to be pack/unpack.
only supposed to be used on sv.setvl
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index bd5f9b76..c9436e9c 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1094,6 +1094,13 @@ class SVP64Asm:
                 destwid = decode_elwidth(encmode[3:])
             elif encmode.startswith("sw="):
                 srcwid = decode_elwidth(encmode[3:])
+            # HACK! using destwid for pack/unpack TODO, separate setvl RM
+            elif encmode == 'pk':
+                destwid = 0b10
+            elif encmode == 'up':
+                destwid = 0b01
+            elif encmode == 'pu':
+                destwid = 0b11
             # element-strided LD/ST
             elif encmode == 'els':
                 ldst_elstride = 1
@@ -1647,6 +1654,12 @@ if __name__ == '__main__':
         'sv.ffmadds 6.v, 2.v, 4.v, 6.v',  # correctly converted to .long
         'svshape2 8, 1, 31, 7, 1, 1',
     ]
+    lst = [
+        'sv.setvl 2, 3, 4, 0, 1, 1',
+        'sv.setvl/pk 2, 3, 4, 0, 1, 1',
+        'sv.setvl/up 2, 3, 4, 0, 1, 1',
+        'sv.setvl/pu 2, 3, 4, 0, 1, 1',
+    ]
     isa = SVP64Asm(lst, macros=macros)
     log("list:\n", "\n\t".join(list(isa)))
     # running svp64.py is designed to test hard-coded lists