From: Mark Mitchell <mark@codesourcery.com>
Date: Mon, 2 Mar 2009 00:29:23 +0000 (+0000)
Subject: 	* config/tc-arm.c (md_assemble): Allow barrier instructions on
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04e2c417f9d55d3a9abf23a78a36a863886b8059;p=binutils-gdb.git

	* config/tc-arm.c (md_assemble): Allow barrier instructions on
	ARMv6-M cores.

	* gas/arm/archv6m.s: Add dmb, dsb, and isb.
	* gas/arm/archv6m.d: Likewise.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b3f22a87b4f..8b8db8ec3b6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-01  Mark Mitchell  <mark@codesourcery.com>
+
+	* config/tc-arm.c (md_assemble): Allow barrier instructions on
+	ARMv6-M cores.
+
 2009-03-01  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>
 
 	* configure: Regenerate.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index a1e5d12ccb0..bb783bdd40e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -14747,7 +14747,8 @@ md_assemble (char *str)
 	  /* Implicit require narrow instructions on Thumb-1.  This avoids
 	     relaxation accidentally introducing Thumb-2 instructions.  */
 	  if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
-	      && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
+	      && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
+		   || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
 	    inst.size_req = 2;
 	}
 
@@ -14805,7 +14806,8 @@ md_assemble (char *str)
 	 This is overly pessimistic for relaxable instructions.  */
       if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
 	   || inst.relax)
-	  && !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
+	  && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
+	       || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
 	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
 				arm_ext_v6t2);
     }
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 31c1dd0d772..69d31f497d8 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2009-03-01  Mark Mitchell  <mark@codesourcery.com>
+
+	* gas/arm/archv6m.s: Add dmb, dsb, and isb.
+	* gas/arm/archv6m.d: Likewise.
+
 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 
 	* gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests.
diff --git a/gas/testsuite/gas/arm/archv6m.d b/gas/testsuite/gas/arm/archv6m.d
index 31d06a31584..2ad48a769e9 100644
--- a/gas/testsuite/gas/arm/archv6m.d
+++ b/gas/testsuite/gas/arm/archv6m.d
@@ -13,3 +13,6 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> bf40      	sev
 0[0-9a-f]+ <[^>]+> 4408      	add	r0, r1
 0[0-9a-f]+ <[^>]+> 46c0      	nop.*
+0[0-9a-f]+ <[^>]+> f3bf 8f5f 	dmb	sy
+0[0-9a-f]+ <[^>]+> f3bf 8f4f 	dsb	sy
+0[0-9a-f]+ <[^>]+> f3bf 8f6f 	isb	sy
diff --git a/gas/testsuite/gas/arm/archv6m.s b/gas/testsuite/gas/arm/archv6m.s
index 158b6a6d936..013bba915fd 100644
--- a/gas/testsuite/gas/arm/archv6m.s
+++ b/gas/testsuite/gas/arm/archv6m.s
@@ -14,3 +14,7 @@ foo:
 	sev
 	add r0, r0, r1
 	nop
+	dmb
+	dsb
+	isb
+