From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 9 Jul 2020 18:59:45 +0000 (+0100)
Subject: DIV overflow needs to be copied into both bits of XER.ov
X-Git-Tag: div_pipeline~132
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=04e6a8d1ae5b8a08f5904d4847453fadf25303eb;p=soc.git

DIV overflow needs to be copied into both bits of XER.ov
(OV, OV32)
---

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index 9eb16f6c..0af52151 100644
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -71,7 +71,7 @@ class DivOutputStage(PipeModBase):
                                   | ((abs_quotient == sign_bit_mask)
                                      & ~self.quotient_neg))
             with m.Else():
-                comb += xer_ov.eq(overflow)
+                comb += xer_ov.eq(Repl(overflow, 2)) # set OV _and_ OV32
 
         with m.If(op.is_32bit):
             calc_overflow(self.i.dive_abs_ov32, 0x80000000)